VIP Central

Archive for September 2015

 

Protocol Debug for Complex SoCs

Here, Bernie DeLay, group director for Verification IP R&D at Synopsys, talks to Ed Sperling of Semiconductor Engineering about the challenges of debugging protocols in complex SoCs. You can learn more about our VIPs at Verification IP Overview.

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Posted in AMBA, DDR, Debug, Methodology, PCIe, Processor Subsystems, Storage, USB | Comments Off on Protocol Debug for Complex SoCs

 

MIPI UniPro for PCIe Veterans

The MIPI Unified Protocol (UniPro) specification defines a layered protocol for interconnecting devices and components within mobile device systems. It is applicable to a wide range of component types including application processors, co-processors, and modems. MIPI UniPro powers the JEDEC UFS, MIPI DSI2 and MIPI CSI3 applications. As of now, MIPI UniPro has been adopted the […]

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Posted in Data Center, Interface Subsystems, Methodology, MIPI, Mobile SoC, MPHY, PCIe, Unipro | Comments Off on MIPI UniPro for PCIe Veterans

 

The Synopsys NVMe VIP: A High Level View

Overview NVM Express or the Non-Volatile Memory Host Controller Interface (its prior name was NVMHCI, now shortened to NVMe) is a host-based software interface designed to communicate with Solid State storage devices across a PCIe fabric. The current Synopsys NVMe Verification IP (VIP) is a comprehensive testing vehicle which consists of two main subsystems – […]

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Posted in MPHY, NVMe, PCIe, Storage, SystemVerilog | Comments Off on The Synopsys NVMe VIP: A High Level View

 

Verifying and Debugging Storage Protocols: SATA

In this video, Synopsys Applications Consultant, Vijay Akkaraju, describes the evolving  Storage ecosystem, the challenges of verifying storage protocol based system, and how Synopsys’ SATA Verification IP can support you in verifying and debugging your designs efficiently and effectively. You can learn more about VC Verification IP for SATA here.

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Posted in Debug, SATA, Storage | Comments Off on Verifying and Debugging Storage Protocols: SATA

 

Skip Initialization for DDR VIP Models

In the blog Seamless Fast Initialization for DDR VIP Models, we discussed how important it is for Memory VIP simulations to have the option of going through the process of Reset and Initialization fast, and get to the IDLE state and start reading and writing to memory location. We presented one way to achieve this by […]

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Posted in DDR, Memory, Mobile SoC, Processor Subsystems | Comments Off on Skip Initialization for DDR VIP Models