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Seamless Fast Initialization for DDR VIP Models

DDR verification is one of the most critical and complex tasks in any SoC as it involves a controller sitting inside the DUT and an external DDR memory sitting outside the DUT on board. Here we will discuss fast initialization for DDR VIP models.

You can learn more about Synopsys Memory VIP here.

As per the JEDEC standard JESD79-4, Section 3.3.1, RESET_n needs to be maintained for a minimum of 200us. In simulation time, this value is a very long time. Furthermore, if the user’s testbench violates this timing, the Memory VIP will flag it as a UVM_ERROR and fail the simulation. Even though this violation is flagged as an error, it doesn’t affect the behavior of the VIP model.

DDR-init

There are a number of ways to get around this violation. In this blog, we will discuss one of these ways.

The Synopsys Memory VIP has an initialization feature called Fast Initialization, also known as, scaled down initialization. The intention of this feature is to allow control for overriding the initialization parameters to speed up the initialization process. The new values, whether they are set by default or customized by the user, enable faster initialization times without asserting any checker violations. Also, it doesn’t affect the initialization behavior of the model. This feature is only available for front door access – vs. backdoor access. We will discuss types of Memory VIP access in subsequent blog posts.

There are two ways to scale down the initialization parameters. One is set by using default values, and another by customization.

As per the standard, the following are the expected values:

min_cke_high_after_reset_deasserted_in_pu_and_res_init_time_ps = 500000000
min_reset_pulse_width_in_pu_ps = 200000000

Using the default approach, one may call the function “set_scaled_initialization_timings()” from the build_phase of the configuration object. That function call will scale down the timing parameters to the assigned values below without triggering checker violations:

min_cke_high_after_reset_deasserted_in_pu_and_res_init_time_ps = 500000
min_reset_pulse_width_in_pu_ps = 200000

To customize the values, the user may set their own customized values and then set the flag “scaled_timing_flag”. The VIP will get configured to the user provided values. As such:

For Discrete Devices:

// cfg handle of the svt_ddr_configuration class

// Pass the cfg to the DDR Discrete Device component by using // the config_db mechanism.

cfg.timing_cfg.min_cke_high_after_reset_deasserted_in_pu_and_res_init_time_ps = 500000;

cfg.timing_cfg.min_reset_pulse_width_in_pu_ps = 200000;

cfg.timing_cfg. tPW_RESET_ps = 100000;

cfg.timing_cfg.scaled_timing_flag = 1;

For DIMM Models:

// dimm_cfg is handle of svt_ddr_dimm_configuration

foreach(dimm_cfg.data_lane_cfg[i]) begin

  foreach(dimm_cfg.data_lane_cfg[i].rank_cfg[j]) begin

    dimm_cfg.data_lane_cfg[i].rank_cfg[j].timing_cfg.min_cke_high_after_reset_deasserted_in_pu_and_res_init_time_ps = 500000;

    dimm_cfg.data_lane_cfg[i].rank_cfg[j].timing_cfg.min_reset_pulse_width_in_pu_ps = 200000;

    dimm_cfg.data_lane_cfg[i].rank_cfg[j].timing_cfg.tPW_RESET_ps = 100000;

    dimm_cfg.data_lane_cfg[i].rank_cfg[j].timing_cfg.scaled_timing_flag = 1;

  end

end

Authored by Nasib Naser

You can learn more about Synopsys Memory VIP here.