Here, we describe how easy it is to integrate and validate a SoundWire design using Synopsys SoundWire VIP Test Suite. Often Verification IP and design integration require in-depth understanding of the protocol and methodology. This requires significant investment of time in building the expertise in-house. To accelerate the process, Synopsys’ Soundwire VIP solution is written in 100% […]
DDR verification is one of the most critical and complex tasks in any SoC as it involves a controller sitting inside the DUT and an external DDR memory sitting outside the DUT on board. Here we will discuss fast initialization for DDR VIP models. You can learn more about Synopsys Memory VIP here. As per the […]
In a recent post, Paul Graykowski introduced Synopsys VIP for PCIe Gen4. To dive deeper into the verification closure process, you can now register for our Webinar on August 14th here. Today’s PCIe verification engineers have to tradeoff between verification completeness and shrinking to market complicated even further with the new Gen4 specification. Synopsys VC […]
Here, Paul Graykowski, Corporate Applications Engineer at Synopsys, describes what our Verification IP for PCIe Gen4 can do for you.