SoC Leaders Verify with Synopsys: DAC 2015 Verification Luncheon

Featuring speakers from Altera, AMD, ARM, Cavium and Freescale

During DAC 2015, Synopsys hosted a luncheon event at DAC in San Francisco, CA.

Michael Sanie, senior director of verification marketing at Synopsys kicked things off by highlighting the Synopsys Verification Continuum and several key next-generation technologies that are in production and address the need to “Shift-Left” for faster time-to-market. These technologies include Verification Compiler, a broad Verification IP portfolio, the industry’s fastest emulation system ZeBu Server-3, and Verdi, the industry’s de facto SoC debug environment.

Later, a panel of SoC industry experts from Altera, AMD, ARM, Cavium and Freescale shared viewpoints on managing the growing verification complexity and how their leading SoC design teams have achieved success by collaborating with Synopsys.

Carlos Velasco, senior manager, SoC Design Verification Group at Altera described the challenges of verifying and debugging their SoC FPGA. He described their system verification environment, the need for verifying their configuration architecture and SoC Topology, and how Synopsys’ native SystemVerilog technology with full UVM support along with a full range of Verification IP has served them well.

Alex Starr, fellow & pre-silicon solutions architect at AMD painted a picture about rethinking the cost of verification. He talked about verification complexity; the importance of methodology; and how emulation with ZeBu and Verdi facilitate hardware-software debug.

Alan Hunter, senior principal design engineer at ARM described the shift-left they have been able to achieve for over 17 years working closely with Synopsys. He described statistical methods, IP-focused system verification, debug and low power verification technologies.

Jim Ellis, director of engineering at Cavium described how they have been addressing the unique verification challenges presented by their ThunderX ARM Processors.  He talked about how they were able to shift-left with virtualization, IP and VIP reuse, standardizing their verification flow with VCS, UVM and incorporating Certitude and VC Formal into their flow.

Robert Oshana, director of software R&D, Digital Networking at Freescale talked about how reference software has been growing a lot faster than Moore’s Law prediction, and how emulating with ZeBu has supported them in their hardware-software debug flow.

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