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VIP Central
Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP
Posted by VIP Experts on June 30, 2015
Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.
You can learn more about our VIPs at Verification IP Overview.
This post is filed under AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM.
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