DAC 2015, San Francisco: Must-See Verification Sessions

It’s going to be an exciting week for  designers and verification engineers at the Design Automation Conference in San Francisco this week. Here’s a list of activities we recommend:

Tuesday June 9th 

• 7:30am – 9 am: Accellera Breakfast and Panel Discussion: Design and Verification Standards in the Era of IoT (Moscone Room 220)
• 9:00am – 9:15am: Moore’s Law at 50: No End in Sight by Vivek Singh, Intel Fellow (Moscone Gateway Ballroom)
• 10:30am – 11:30am: Session 15: IP Verification Track (Moscone 101)
• 11:30am – 1:30pm: Verification Luncheon: SoC Leaders Verify with Synopsys (Park Central Hotel – formerly Westin, Metropolitan Ballroom I: 50 Third Street, San Francisco, CA 94103)
• 1:30pm – 3pm: Session 25: Designer & IP Track: Innovative Front-End Design and Validation at System Level (Moscone 105)
• 4:30pm – 6pm: Session 31: DAC Designer and IP Track Poster Session (Moscone Exhibit Floor)

Wednesday June 10th

• 11:30am – 12:15pm: Fireside Chat with Aart de Geus (DAC Pavilion: Booth 311)
• 1:30pm – 3pm: Session 45: Designer Track: The Expanding World of System Verification (Moscone 105)
• 4:30pm – 6pm: Session 52: Designer Track: New Directions in Static and Formal Methods (Moscone 105)
• 4:30pm – 6pm: Session 48: Panel: Scalable Verification: Evolution or Revolution? (Moscone 304)