VIP Central

Archive for June 2015

 

Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans. You can learn more […]

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Posted in AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM | Comments Off on Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

 

Verifying MIPI interfaces in SoCs

It is estimated that every smartphone now uses some aspect of the MIPI standards. Last year, one billion phones, and about 6 to 7 billion phone ICs, included a MIPI interface of some sort. MIPI interfaces, especially for cameras and displays, have spread beyond the mobile world into other markets, such as automotive, industrial, medical, […]

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Posted in Audio, Interface Subsystems, Methodology, MIPI, Mobile SoC, UFS | Comments Off on Verifying MIPI interfaces in SoCs

 

Hands-on Memory Verification IP Workshops

Synopsys Memory Verification IP is modeled natively in SystemVerilog and supports the common verification standard UVM. Our models support 100% of the memory standard as specified by JEDEC. Now you can take a deep dive into our VIP solutions at no cost with a hands-on workshop. The workshop will highlight and demonstrate how you can […]

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Posted in DDR, eMMC, HBM, LPDDR, Memory, Methodology, ONFi, UFS | Comments Off on Hands-on Memory Verification IP Workshops

 

DAC 2015, San Francisco: Must-See Verification Sessions

It’s going to be an exciting week for  designers and verification engineers at the Design Automation Conference in San Francisco this week. Here’s a list of activities we recommend: Tuesday June 9th  7:30am – 9 am: Accellera Breakfast and Panel Discussion: Design and Verification Standards in the Era of IoT (Moscone Room 220) 9:00am – 9:15am: […]

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Posted in Methodology, SystemVerilog, UVM | Comments Off on DAC 2015, San Francisco: Must-See Verification Sessions

 

Performance Advantages of Synopsys VIP

In this video, you will learn how several users are benefiting from the performance advantage of using Synopsys VIP  http://bit.ly/1Kau83g You can learn more about our VIPs at Verification IP Overview

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Posted in Debug, SystemVerilog, Test Suites, UVM | Comments Off on Performance Advantages of Synopsys VIP

 

Benefits of MIPI Soundwire

In MIPI Soundwire: Digital Audio Simplified, we mentioned that digital audio formats, including Pulse Code Modulation (PCM) and Pulse Density Modulation (PDM), are target applications for MIPI Soundwire. Later, we discussed Digital Audio Streams and Channels. Here, we will talk about the merits MIPI Soundwire protocol has over other available digital audio interfaces. For more information on MIPI Soundwire, you can download our whitepaper Major […]

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Posted in Audio, Interface Subsystems, Methodology, MIPI, Mobile SoC, Soundwire | Comments Off on Benefits of MIPI Soundwire