Verification Central


Memory VIP Challenges

Behavioral Memory Models have been used for verification purposes for several years now. In the early days, modeling technology didn’t add much value to the usage model as designs were simple.

With increasing design complexity, and demand for more functionality driving SoC complexity and cost, memory verification models need to morph into a state that can ensure that memory requirements meet the demand of the design. A realistic way to achieve this is to develop these models in the most commonly used design and verification language, SystemVerilog.

You can find more information on Synopsys Memory VIP at

Synopsys Memory Verification IP is modeled natively in SystemVerilog and supports the common verification standard UVM. Furthermore, these models follow 100% of the Memory standard as specified by Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association, a semiconductor trade and engineering standardization organization.


Many challenges are faced when designers use a memory VIP, whether it is developed in-house or acquired from a third party vendor. These challenges vary from whether the use model is to design a Memory Controller, a DFI, a PHY or using the memory as a dummy memory device to validate other blocks on the SoC. Memories can be discrete such as DDR3 or DDR4, or In-Line such as DIMMs. The challenges encountered vary from usability, to functionality, to configurability. Working closely with users in the field, here is a list that we have created:

  1. Ease of integration
  2. Part selection
  3. Initialization control
  4. Coverage
  5. Protocol and timing checks
  6. Backdoor access
  7. Scoreboard hooks
  8. Debug support
  9. Protocol-centric debug
  10. Synchronized transaction and waveform view

Each challenge will be addressed in a subsequent blog post. So do come back 🙂

Authored by Nasib Naser

You can find more information on Synopsys Memory VIP at