VIP Central

Archive for April 2015

 

PCIe: Monitors and Test Suites

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP Monitor and Test Suites http://bit.ly/1DHIdyQ You can learn more about our VIPs at Verification IP Overview, or download the Datasheet for PCIe and MPCIe.

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Posted in Debug, PCIe, SystemVerilog, Test Suites, UVM | Comments Off on PCIe: Monitors and Test Suites

 

MIPI Soundwire: Pulse Code Modulation (PCM)

In MIPI Soundwire: Digital Audio Simplified, we mentioned that digital audio formats including Pulse Code Modulation (PCM) and Pulse Density Modulation (PDM) are target applications for MIPI Soundwire. For more information on MIPI Soundwire, you can download our whitepaper. In this blog post, we will discuss PCM. PULSE CODE MODULATION Most current digital audio systems (computers, compact […]

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Posted in Audio, Interface Subsystems, Methodology, MIPI, Mobile SoC, Soundwire | Comments Off on MIPI Soundwire: Pulse Code Modulation (PCM)

 

PCIe: Accelerating Debug

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP’s capabilities that will support your efforts to accelerate the debug process: You can learn more about our VIPs at Verification IP Overview, or download the Datasheet for PCIe and MPCIe.

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Posted in Debug, PCIe, SystemVerilog, UVM | Comments Off on PCIe: Accelerating Debug

 

The HDCP 2.2 Authentication Process – an Introduction

When digital content is transmitted, it is susceptible to unauthorized copying and interceptions. Hence protecting content has become an important factor in the transmission of audiovisual content. In 2003, Intel developed an encryption technique called the High-bandwidth Digital Content Protection (HDCP) protocol to protect audio and video data between a transmitter (transmitting the audio visual […]

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Posted in HDCP, HDMI, Methodology | Comments Off on The HDCP 2.2 Authentication Process – an Introduction

 

PCIe VIP: Accelerating Verification

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP’s capabilities that will support your efforts to accelerate the verification process: http://bit.ly/1CWit0q You can learn more about our VIPs at Verification IP Overview, or download the Datasheet for PCIe and MPCIe.

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Posted in Methodology, PCIe, SystemVerilog, UVM | Comments Off on PCIe VIP: Accelerating Verification

 

MIPI Soundwire: Digital Audio Simplified

MIPI Alliance has come up with a new protocol standard for sound interface called SoundWire. SoundWire is a robust, scalable, low complexity, low power, low latency, two-pin (clock and data) multi-drop bus that allows for the transfer of multiple audio streams and embedded control/commands. To understand its specification and design verification needs, it is important […]

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Posted in Audio, Interface Subsystems, Methodology, MIPI, Mobile SoC, Soundwire | Comments Off on MIPI Soundwire: Digital Audio Simplified

 

Freescale and Xilinx Engineers: Managing SoC Verification Complexity

At DVCon 2015, a couple of our key customers shared their viewpoints on how they manage growing verification complexity. This video begins with Michael Sanie highlighting the Synopsys Verification Continuum, and several key technologies that currently address the industry’s need to “Shift-Left” for faster time-to-market. Later, Amol Bhinge of Freescale and Prashanth Gurunath of Xilinx […]

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Posted in AMBA, Audio, Camera, DDR, Debug, DesignWare, Display, HDMI, Interface Subsystems, LPDDR, Methodology, MIPI, Mobile SoC, PCIe, SystemVerilog, Test Suites, USB, UVM | Comments Off on Freescale and Xilinx Engineers: Managing SoC Verification Complexity

 

PCIe Verification IP Overview

In this video, VIP Senior Manager Paul Graykowski of Synopsys gives an overview of the PCI Express Verification IP: http://bit.ly/1DTe6si You can learn more about our VIPs at Verification IP Overview, or download the Datasheet for PCIe and MPCIe.

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Posted in Debug, PCIe, SystemVerilog, Test Suites, UVM | Comments Off on PCIe Verification IP Overview

 

AMBA: Stitch it all up to ACE your Test

The ARM® AMBA4® specification for the connection and management of functional blocks in a system-on-chip (SoC) now features Advanced eXtensible Interface (AXI)™ coherency extensions (ACE)™ in support of multi-core computing. The ACE specification enables system-level cache coherency across clusters of multi-core processors. When planning the functional verification of such a system, these coherency extensions bring […]

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Posted in AMBA, Methodology, SystemVerilog, UVM | Comments Off on AMBA: Stitch it all up to ACE your Test