In my previous blog post, I discussed guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively? Here’s where you can find more […]
In this blog, I describe the necessary steps one has to take while writing a sequence to make sure it can be reusable. Personally, I feel writing sequences is the most challenging part in verifying any IP. Careful planning is required to write sequences without which we end up writing one sequence for every scenario […]
As you may know, USB3.0 has a state machine called LTSSM (Link training and status state machine) which is responsible for Initialization and link training Power management transitions Link error recovery and other connectivity issues. Here’s where you can find more information on our Verification IP. LTSSM has 12 high level states as shown below. In […]
In my previous blog, AMBA based Subsystems: What does it take to verify them?, I had discussed some of the key verification challenges when it comes to verifying complex SOCs based on AMBA based subsystems. It was observed that it would indeed be useful to have an extensible AMBA based verification environment which can be […]
VIP manager Tushar Mattu of Synopsys describes how to program AXI-ACE VIP to generate error scenarios For more information, please check out Verification IP for AMBA 4 AXI.
VIP manager Tushar Mattu of Synopsys gives insights on how to effectively integrate uvm_reg with AXI VIP http://bit.ly/1xboMLS For more information, please check out Verification IP for AMBA 4 AXI.
Recently I worked with a user who was responsible for verifying an AXI interface. This user did not have a UVM background, but was conversant with SystemVerilog. The user was faced with the challenge of learning UVM as well as coming up to speed with an understanding of the VIP: both at the same time, […]
VIP manager Tushar Mattu of Synopsys gives insights on how to effectively use the AXI VIP Debug Port http://bit.ly/18QYPMs For more info, please check out Verification IP for AMBA 4 AXI.
Lately we have seen a trend of serial data transfers in place of parallel data transfer for improved performance and data integrity. One example of this is the migration from PCI/PCI-X to PCI Express. A serial interface between two devices results in fewer number of pins per device package. This not only results in reduced […]