VIP Central

Archive for March 2015

 

Virtual Sequences in UVM: Why, How?

In my previous blog post, I discussed guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively? Here’s where you can find more […]

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Posted in AMBA, Audio, Debug, Interface Subsystems, Methodology, MIPI, Mobile SoC, SystemVerilog, USB, UVM | Comments Off on Virtual Sequences in UVM: Why, How?

 

Reusable Sequences in UVM

In this blog, I describe the necessary steps one has to take while writing a sequence to make sure it can be reusable. Personally, I feel writing sequences is the most challenging part in verifying any IP. Careful planning is required to write sequences without which we end up writing one sequence for every scenario […]

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Posted in Debug, Methodology, SystemVerilog, USB, UVM | Comments Off on Reusable Sequences in UVM

 

Ins and outs of SS Link Training in USB3.0

As you may know, USB3.0 has a state machine called LTSSM (Link training and status state machine) which is responsible for Initialization and link training Power management transitions Link error recovery and other connectivity issues. Here’s where you can find more information on our Verification IP. LTSSM has 12 high level states as shown below. In […]

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Posted in Methodology, SystemVerilog, USB | Comments Off on Ins and outs of SS Link Training in USB3.0

 

How do you Verify the AMBA System Level Environment?

In my previous blog, AMBA based Subsystems: What does it take to verify them?, I had discussed some of the key verification challenges when it comes to verifying complex SOCs based on AMBA based subsystems. It was observed that it would indeed be useful to have an extensible AMBA based verification environment which can be […]

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Posted in AMBA, Methodology, SystemVerilog, UVM | Comments Off on How do you Verify the AMBA System Level Environment?

 

Programming AXI-ACE VIP to Generate Error Scenarios

VIP manager Tushar Mattu of Synopsys describes how to program  AXI-ACE VIP to generate error scenarios For more information, please check out Verification IP for AMBA 4 AXI.

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Posted in AMBA, Debug, SystemVerilog, UVM | Comments Off on Programming AXI-ACE VIP to Generate Error Scenarios

 

How to Integrate uvm_reg with AXI VIP

VIP manager Tushar Mattu of Synopsys gives insights on how to effectively integrate uvm_reg with AXI VIP http://bit.ly/1xboMLS For more information, please check out Verification IP for AMBA 4 AXI.

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Posted in AMBA, Methodology, SystemVerilog, UVM | Comments Off on How to Integrate uvm_reg with AXI VIP

 

Start using AXI VIP with some basic understanding of UVM

Recently I worked with a user who was responsible for verifying an AXI interface. This user did not have a UVM background, but was conversant with SystemVerilog. The user was faced with the challenge of learning UVM as well as coming up to speed with an understanding of the VIP: both at the same time, […]

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Posted in AMBA, Methodology, SystemVerilog, UVM | 1 Comment »

 

How to Use the AXI VIP Debug Port

VIP manager Tushar Mattu of Synopsys gives insights on how to effectively use the AXI VIP Debug Port  http://bit.ly/18QYPMs For more info, please check out Verification IP for AMBA 4 AXI.

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Posted in AMBA, Debug, Methodology, SystemVerilog, UVM | Comments Off on How to Use the AXI VIP Debug Port

 

Power Management of PCIe PIPE Interface

Lately we have seen a trend of serial data transfers in place of parallel data transfer for improved performance and data integrity. One example of this is the migration from PCI/PCI-X to PCI Express. A serial interface between two devices results in fewer number of pins per device package. This not only results in reduced […]

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Posted in Methodology, PCIe | Comments Off on Power Management of PCIe PIPE Interface