Verification Central


Key Advantages of Synopsys Memory VIP Architecture

Following on his recent talk about why Synopsys chose a SystemVerilog Architecture for interface VIP, here Synopsys R&D Director Bernie DeLay talks about how a similar architecture based on SystemVerilog for Memory VIP brings some key advantages for verifying the memory interfaces in your SoC design and memory controller IP: 

Here’s where you can learn more about our Memory VIP