VIP Central

Archive for February 2015

 

How to Integrate AXI VIP into a UVM Testbench

Here, Synopsys VIP manager Tushar Mattu describes how best we can integrate AXI VIP into a UVM Testbench:  http://bit.ly/1Ay3zfb  For more info, please check out Verification IP for AMBA 4 AXI.

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Posted in AMBA, SystemVerilog, UVM | Comments Off on How to Integrate AXI VIP into a UVM Testbench

 

Parameterized Interfaces and Reusable VIP (3 of 3)

This is the third part of a three part series discussing SystemVerilog interfaces and strategies for dealing with parameterization. You can get more information at Synopsys Verification IP and VC Verification IP Datasheet. In the first part of this series, the basic concepts of SystemVerilog interfaces were introduced, and the problems that parameterization of those interfaces introduce to […]

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Posted in Methodology, SystemVerilog, UVM | Comments Off on Parameterized Interfaces and Reusable VIP (3 of 3)

 

Parameterized Interfaces and Reusable VIP (2 of 3)

This is the second part of a three part series discussing SystemVerilog interfaces and strategies for dealing with parameterization. You can get more information at Synopsys Verification IP and VC Verification IP Datasheet. In the first part of this series the basic concepts of SystemVerilog interfaces were introduced and the problems that parameterization of those interfaces introduce to […]

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Posted in Methodology, SystemVerilog, UVM | Comments Off on Parameterized Interfaces and Reusable VIP (2 of 3)

 

AMBA based Subsystems: What does it Take to Verify Them?

Let’s look at a typical AMBA based subsystem in the SOCs that we find today: From this picture, what is clear to me is a preponderance of multiple AMBA components of different flavors (AXI3/4, ACE, AHB, APB). So, even if we have all of the different VIPs to represent these .different flavors, it is not […]

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Posted in AMBA, Methodology | 1 Comment »

 

Accelerating Memory Debug

Following on his recent talk about Key Advantages of Synopsys Memory VIP Architecture, here Synopsys R&D Director Bernie DeLay talks about protocol-aware debug for memories: a single environment to simultaneously visualize transactions, state machines, and memory arrays   http://bit.ly/1KKRmMn Here’s where you can learn more about our Memory VIP

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Posted in AMBA, DDR, Debug, LPDDR, Methodology | Comments Off on Accelerating Memory Debug

 

Video Frame Transmission in MIPI-DSI

DSI is a high speed serial interface targeted to reduce the cost of display sub-systems in a mobile device by transferring the data to the display module in real time without storing the data in the device. However this means that the data has to be sent with proper timing information. The most important aspect […]

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Posted in Display, DSI, MIPI | Comments Off on Video Frame Transmission in MIPI-DSI

 

Key Advantages of Synopsys Memory VIP Architecture

Following on his recent talk about why Synopsys chose a SystemVerilog Architecture for interface VIP, here Synopsys R&D Director Bernie DeLay talks about how a similar architecture based on SystemVerilog for Memory VIP brings some key advantages for verifying the memory interfaces in your SoC design and memory controller IP:  http://bit.ly/1zaAcip  Here’s where you can learn […]

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Posted in DDR, LPDDR, Methodology, SystemVerilog | Comments Off on Key Advantages of Synopsys Memory VIP Architecture

 

A Strategy To Verify an AXI/ACE Compliant Interconnect (3 of 4)

In the last post of this series, I wrote about basic coherent testing. In this post, I will discuss some of the nuances of the specification relative to accesses to overlapping addresses. Since multiple masters may be sharing the same location and the data could be distributed across the caches of different masters, this is an […]

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Posted in AMBA | Comments Off on A Strategy To Verify an AXI/ACE Compliant Interconnect (3 of 4)