VIP Central

Archive for January 2015

 

Spec-based Coverage Closure with Synopsys VIP

Here, Synopsys R&D Director Bernie DeLay talks about achieving coverage closure for protocol compliance checking and integration testing by utilizing the built-in verification plans and functional coverage provided with VC VIP. He describes configuration-aware coverage: how it correlates with the user’s specification:  http://bit.ly/1EqRsIj You can learn more about our Verification IP here.

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Posted in Debug, Methodology, SystemVerilog | Comments Off on Spec-based Coverage Closure with Synopsys VIP

 

Parameterized Interfaces and Reusable VIP (1 of 3)

This is the first part of a three part series discussing SystemVerilog interfaces and strategies for dealing with parameterization. You can get more information at Synopsys Verification IP and VC Verification IP Datasheet. Background SystemVerilog based verification introduces the concept of interfaces to represent communication between design blocks.  In its most elemental form a SystemVerilog interface is just […]

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Posted in Methodology, SystemVerilog, UVM | 2 Comments »

 

Overcoming the Protocol Debug Challenge

In this talk, Synopsys R&D Director Bernie DeLay describes advanced methods for protocol-aware debug and how to use advanced debug techniques like protocol abstraction in a unified debug environment to find the root cause of errors for the most complex of bus and interface protocols:  http://youtu.be/FFO5vtH6QDI Here’s where you can find more information on our Verification IP

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Posted in Debug, USB | Comments Off on Overcoming the Protocol Debug Challenge

 

Expectations of a Verification IP User: Transaction Modeling

In my blog posts, I will be sharing my expectations from a Verification IP. I will begin with Transaction Modeling. Having played a role in both developing as well as in using Verification IPs, I consider the transaction class to be the most important component of a VIP. The quality of a transaction class defines […]

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Posted in AMBA, Methodology, SystemVerilog, UVM | Comments Off on Expectations of a Verification IP User: Transaction Modeling

 

SystemVerilog Protocol Compliance: Why Source-code Test Suites?

Here, Bernie DeLay explains the architecture and scope of the SystemVerilog source-code test suites included with the Synopsys VIP titles, and how they minimize the effort associated with protocol compliance testing. He uses a USB VIP in a DesignWare environment with AXI as an example  http://bit.ly/1BHUgQg

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Posted in AMBA, DesignWare, Methodology, SystemVerilog, Test Suites, USB, UVM | Comments Off on SystemVerilog Protocol Compliance: Why Source-code Test Suites?

 

VIP Architecture: Why Native SystemVerilog and UVM?

Four years ago, we talked to several key customers, and decisively moved all our VIP development to an architecture based on SystemVerilog and UVM.  In this short video, you can learn about the benefits of using such VIP for verifying your SoCs: ease-of-use, productivity and accelerated coverage closure  http://bit.ly/1CDjImJ

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Posted in Methodology, SystemVerilog, UVM | Comments Off on VIP Architecture: Why Native SystemVerilog and UVM?

 

SystemVerilog Test Suites Accelerate IP-to-SoC Reuse

Verifying complex SoCs takes a lot of effort. Our user surveys show that around 70% of the engineering resource involved in taping out a complex SoC is spent on verification, with half of that time consumed by debug. You can get more information at VIP Test Suites. Without a well-thought-out verification environment, verification teams waste […]

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Posted in Methodology, PCIe, SystemVerilog, Test Suites | Comments Off on SystemVerilog Test Suites Accelerate IP-to-SoC Reuse

 

Simplifying the Usage of UVM Register Model

When I began using UVM RAL, I could not understand what the UVM base class library had to say about updating the values of desired value and mirror value registers. I also felt that the terms used do not reflect the intent precisely. After spending some time, I came up with a table which helped […]

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Posted in Methodology, SystemVerilog, UVM | Comments Off on Simplifying the Usage of UVM Register Model