VIP Central

Archive for 2015

 

Celebrating the Holiday Season with VIPs

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Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB | Comments Off on Celebrating the Holiday Season with VIPs

 

Debugging Memory Protocols with the Verdi Protocol Analyzer

Debug continues to be one of the biggest hurdles faced by design and verification engineers. While designing a system that requires close interactions with memories, engineers often rely on print statements or waveform viewers to decipher signal behaviors over time, and/or their relationship relative to other signals over time. While this kind of ad-hoc debugging helps in understanding the behavior of a single signal, it does not work well when debugging protocols.

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Posted in DDR, Debug | Comments Off on Debugging Memory Protocols with the Verdi Protocol Analyzer

 

PCIe Spread Spectrum Clocking (SSC) for Verification Engineers

Many of us who work primarily in digital verification and design are shielded from physical layer details. Only a handful of specialists closely follow these details. So for the rest of us, verifying and debugging Spread Spectrum Clocking (SSC) can be a daunting task.

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Posted in Methodology, PCIe | Comments Off on PCIe Spread Spectrum Clocking (SSC) for Verification Engineers

 

NVMe VIP Architecture: Host Features

In my last post, I covered a basic NVMe VIP test-case including some basic setup, sending a command and receiving a completion. Here, we’ll look at a few more NVMe commands, touching on some of the features and capabilities of the VIP.

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Posted in Methodology, NVMe, PCIe, UVM | Comments Off on NVMe VIP Architecture: Host Features

 

MIPI I3C VIP Accelerates Scalable Sensor Interfaces on Mobile Devices

As sensors continue to get smaller, more powerful and cheaper, smartphones and other mobile devices incorporate over ten sensors to create self-aware devices. For instance, most recent models of Apple and Samsung handheld devices use several sensors to perform some of their coolest interface tricks: proximity sensor, accelerometer (motion sensor), ambient light sensor, moisture sensor, gyroscope, thermometer and magnetometer (compass). These sensors enable key capabilities for users including location services, health apps, fingerprint scanning and sophisticated gaming while optimizing power usage and WiFi access.  

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Posted in Debug, I3C, Mobile SoC, SystemVerilog, UVM | Comments Off on MIPI I3C VIP Accelerates Scalable Sensor Interfaces on Mobile Devices

 

Keeping Pace with Memory Technology using Advanced Verification

My latest webinar, Keeping Pace with Memory Technology using Advanced Verification, begins by taking the audience back in time. To a time when memories had low density, slow performance, and required expensive silicon real estate. Then I fast forward back to the future when memory technologies have evolved to support huge densities, blazing fast speeds while keeping power consumption low, and all this within very small geometry.

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Posted in DDR, DFI, Flash, HBM, HMC, LPDDR | Comments Off on Keeping Pace with Memory Technology using Advanced Verification

 

First Ethernet 400G VIP to Enable Next-Gen Networking and Communications SoCs

On Monday, Synopsys announced the availability of the industry’s first verification IP (VIP) and source code test suite to support the proposed IEEE P802.3bs/D1.0 Ethernet 400G standard (400GbE). To understand how it will enable next generation networking and communication systems, we take a look at the evolution of the Ethernet.

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Posted in Data Center, Ethernet, Methodology, SystemVerilog, Test Suites, UVM | Comments Off on First Ethernet 400G VIP to Enable Next-Gen Networking and Communications SoCs

 

Accelerate your MIPI CSI-2 Verification with a Divide and Conquer Approach

MIPI Alliance’s CSI-2 (Camera Serial Interface) has achieved widespread adoption in the smartphone industry for its ease-of-use and ability to support a broad range of imaging solutions. MIPI CSI-2 v1.3, which was announced in February 2015, also offers users the opportunity to operate CSI-2 on either of two physical layer specifications: MIPI D-PHY, which CSI-2 has used traditionally, as well as MIPI C-PHY, a new PHY that MIPI first released in September 2014. Products may implement CSI-2 solutions using either or both PHYs in the same design. MIPI CSI-2 v1.3 with C-PHY provides performance gains and increased bandwidth delivery for realizing higher resolution, better color depth, and higher frame rates on image sensors while providing pin compatibility with MIPI D-PHY.

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Posted in C-PHY, Camera, CSI, D-PHY, MIPI | Comments Off on Accelerate your MIPI CSI-2 Verification with a Divide and Conquer Approach

 

Synopsys AMBA 5 AHB5 Verification IP: What’s It All About?

This week, at ARM Techcon 2015, Synopsys announced the availability of our VC Verification IP for the new ARM AMBA 5 Advanced High-Performance Bus 5 (AHB5) interconnect. The AHB5 protocol is an update to the widely adopted AMBA 3 AHB3 specification. It extends the TrustZone security foundation from the processor to the entire system for embedded designs. AHB5 supports the newly announced ARMv8-M architecture which drives security into the hardware layer to ensure developers have a fast and efficient way of protecting any embedded or Internet of Things (IoT) device.

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Posted in AMBA, SystemVerilog, Test Suites | Comments Off on Synopsys AMBA 5 AHB5 Verification IP: What’s It All About?

 

ARM TechCon: Optimize SoC Performance with Synopsys Verification IP and Verdi Unified Debug

Companies developing complex ARM-based SoC designs have to constantly keep up with evolving interface standards and proliferating protocols a recurring problem that is resource-intensive and time-consuming. Orchestrating these multiple protocols is critical to extracting maximum SoC performance a key competitive differentiator. Achieving high performance while ensuring correct protocol behavior is best addressed by a combination of transaction-based, protocol-aware verification and debug environments. Synopsys VIP coupled with the Verdi unified debug platform spans verification planning, simulation debug, coverage, HW-SW debug and emulation debug, and helps tackle this challenge end-to-end.

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Posted in AMBA, CHI, Debug, Methodology | Comments Off on ARM TechCon: Optimize SoC Performance with Synopsys Verification IP and Verdi Unified Debug