Verification Central


10 Things to Know about Memory VIP

As designers, we face many challenges during the SoC design cycle: the architecture goes through several iterations; bus speeds can vary; peripherals may be added or removed; the software becomes more complex. How can we ensure that our selection of memory will keep up with all these changes, some of which can occur a few weeks before functional closure?

We recently held a technical webinar at Synopsys to discuss how feature-rich, native SystemVerilog memory VIP can accelerate the verification of memory interfaces on most complex designs, focusing on 10 key areas where productivity is improved.


What You Will Learn from our Webinar:

  • Dynamic part selection; no need for re-compilation when selecting new part
  • Intelligent, built-in JEDEC compliant Protocol and timing checks
  • Pre-defined CoverGroups for Memory State transition, training and power down modes, and more
  • Direct testbench access to the Memory Core for peek, poke, and set/get/clear any memory location attributes
  • Error injections into transactions
  • Synchronized debug between transactions and signals