VIP Central

We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols  and applications ranging from AI, Cloud, Display, Storage and […]

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HDMI 2.1/2.0 bring significant improvements over previous versions in terms of speed, data integrity, and mode of data transmission. For more details on how HDMI has evolved, read our previous blog – HDMI 1.4 to 2.1: How it Became the Most Popular Display Interface. Scrambling is one of the most important features introduced in HDMI […]

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Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs, requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in latest PCIe, USB, DP, and SATA protocol specifications, as […]

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Next generation SoC designs require faster coherent interconnects for high performance applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology. CCIX (Cache Coherent Interconnect for Accelerators), a new protocol standard, provides benefits of cache coherency and peer processing which enables the faster interconnect. CCIX is designed smartly to […]

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DSC has enabled the use of high resolution displays in televisions, PC monitors, mobiles, and automotive infotainment systems. It provides a high quality, low latency algorithm to resolve the bottleneck of high bandwidth requirements needed to support the high resolution. In our previous blog post, 10K Resolution at 120Hz Display: A Reality Today with DSC […]

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We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance […]

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This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. Synopsys provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos. The […]

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The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies – DDR5, LPDDR5. Like their predecessors, the latest memory technologies also use DFI, a standard interface between memory controller and PHY, to reduce the integration cost and increase performance and data throughput efficiency. DFI also has […]

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The HDMI forum officially released HDMI 2.1 in November, 2017. Gamers around the world saw a new ray of hope in the new features announced in the latest specification – “Enhanced refresh rate features ensure an added level of smooth and seamless motion and transitions for gaming, movies and video” (Ref: HDMI Forum releases v2.1 […]

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Debugging the complex serial protocols is the biggest challenge verification engineers face. It’s one of the most time and effort consuming activity affecting the schedule of every project. Traditional debug methodologies use a combination of loosely connected waveforms, log files, messages, and documentation, which are insufficient for productive debugging. Debugging SoC and block level issues […]

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