VIP Central

The ordering of memory transactions in AMBA protocol is a significant requirement, i.e. the sequence of memory updates/accesses must follow a defined ordering as per the specification. Ordering is important for synchronization events by a processor with respect to retiring load/store instructions. AMBA ACE barrier transactions are used for maintaining the memory ordering across a […]

Continue Reading...

    Synopsys next generation Verification IP (VIP) provides verification engineers access to the industry’s latest protocols, interfaces and memories required to verify their SoC designs. Synopsys VIP has a proven record of 20+ years of successful VIP deployments. Continuing our endeavor to keep engineers up-to-date with latest happenings in Verification IP and Test Suites, […]

Continue Reading...

The JESD204B specification is the newer version published by JEDEC standard for data converters and logic devices. If you are working on high-speed data capture designs using an FPGA, you’ve would have heard the new buzz word, ‘JESD204B’. This newer version provides significant benefits over LVDS and CMOS interfaces, as it includes an easier layout […]

Continue Reading...

Every hot selling multimedia device today has enviable specifications, but the first thing the user experiences is the display quality. Displays are coming closer to our natural vision by every passing day, thanks to the increasing resolution, and color depths. UHD displays with 4k resolution are being adopted rapidly, and demand for even higher 8k […]

Continue Reading...

Can your PCB handle speed up to 12.5Gbps, surprised, right? The JESD204B standard provides bit rates up to 12.5Gbps for serial interfaces. This upgrade allows designers to use fewer transceivers on FPGA/ASIC thereby reducing the I/O count and packaging size. The new standard is being adopted rapidly in high-speed data converter applications such as wireless […]

Continue Reading...

If you are currently using or consider using JEDEC UFS protocol in your next design you might face several verification challenges.  The following blog will talk about 7 of the biggest challenges of UFS stack verification. With the fact that people are moving to reduced pin count and increased speed, an MPHY based stack has […]

Continue Reading...

Sensors are everywhere surrounding us at home, office, cars, industry and everything else we are using today. It all started with the thermostat and first motion sensor used for an alarm system invented somewhere in 1950s. Over the period of time, rapid increase of sensors used across various applications created significant challenges, there was a need […]

Continue Reading...

In our previous blog on SAS, we discussed about SAS 24G new encoding and features. In the series of SAS blogs, here we shed some light on other generations of SAS that are still hot in the market. SAS was announced in 2004, supporting data rates till 3Gbps for SAS drives and was compatible with […]

Continue Reading...

Advancement in Memory technologies and the demand for faster and higher density configuration leaves verification engineers in a limbo. The Memory world is debating the next wave of memory protocols and technologies such as Next Generation DDR, HBM, and NVDIMM: DDR: Wishfully the next generation DDR specifications will bring many benefits to computers. With faster and […]

Continue Reading...

The two fundamental requirements of every mobile device is speed and power, with the biggest challenge being that both are inversely proportional to each other. One simply cannot have both, because with higher speed comes higher power consumption. With the ever increasing demand for higher resolution graphics and media to enrich the user experience, there […]

Continue Reading...