Verification consumes most of the compute resources in a typical data center for a semiconductor design company. Simulation comprises one of the largest, if not the largest, workloads in this mix. To maximize the likelihood of first silicon success, development teams often increase the volume of simulation jobs they run in preparation for tape-out. However, this effort is often limited by the compute resources that customers can bring to bear on the task.
SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.
Verifications account for almost 70% of the time and resources consumed during chip development. Moving some or even all of logic simulation to cloud allows customers to free up valuable on-premises resources for other workloads. The deployment of Synopsys’ functional verification solutions on the AWS cloud platform enables accelerated development and verification of breakthrough connectivity technology and SoCs. AWS cloud enables users to take advantage of elastic infrastructure resources to address the increasing capacity requirements for semiconductor simulations.
Join us March 1- 4 at DVCon US 2021, to learn how we help customers optimize chips for power, performance, and cost and cut months off their project schedules.
In the CXL ecosystem the host software uses enumeration as the first step to discover CXL devices connected in the system.
Welcome to the wonderful and cryptic world of secured traffic with CXL being the latest specification to adopt it. CXL2.0 specification introduces integrity & data encryption (IDE) schematics for both CXL.io & CXL.cachemem protocols. CXL.io pathway uses PCIe specification defined IDE, while CXL.cachemem related updates are introduced in CXL2.0 specifications. In this blog we’ll provide a broad overview of what a secure setup looks like and the strategies adopted by CXL for the same.
Color space is a very powerful tool that comes in handy when capturing, transmitting and reproducing color back to the human eye. Systems such as cameras, GPUs, transmission cables (HDMI/DP), and monitors use color space metrics to preserve and transform color. This technology helps map real colors to the color model’s discrete values.
Lately television lovers across the world have an even better reason to be glued to the small screens, as 8K Ultra HD TVs have made their way to the market. The HDMI forums most recently released specification, v2.1, explains “higher video resolutions support a range of high resolutions and faster refresh rates including 8K60Hz and 4K120Hz for immersive viewing and smooth fast-action detail…” Most of us are familiar with the word “resolution”, but do we really know this term well?
JEDEC recently announced the ratification of JESD79-5 DDR5 SDRAM to support the standardization of next-generation memory devices, catering to demand from rapid expansion in high performance computing and data center applications. This new standard promises to deliver 2X memory bandwidth, 4X larger density dies, and much improved power efficiency (1.1V Vdd). The DDR5 DIMM will operate in dual-channel mode all on its own, with two 40-bit fully independent sub-channels on the same module.
In today’s digital age, networking requirements have become increasingly crucial. The possibility of unauthorized access to networks and confidential information have increased the need for secure network access.
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.