Posted by patsheridan on July 28, 2016
In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory.
In March we teamed up with Micron, a global supplier of high performance, low power memory technologies, to present a tutorial at SNUG Silicon Valley (see proceedings) explaining the practical steps system designers can take to convert static, spreadsheet-based power model information for DDR memories into dynamic, IEEE 1801-2015 UPF 3.0 power models that can be simulated together with their SoC architecture in Synopsys Platform Architect MCO.
For DDR4 memory, there are four power domains defined by the Micron DRAM Power Calculator:
The UPF 3.0 system-level power model in Platform Architect MCO is created from this information and capture the power states, power state transitions, power expressions, and inputs for each domain.
As you can tell from the blog title, today we’ll look a bit deeper into DDR Background Power. The chart below shows the average power consumption of a DDR4 memory subsystem during the execution of the SoC application. The top half of the stacked bars shows how the DDR power consumption varies as the application runs to completion. Meanwhile the bottom half shows the constant burn of Background Power, consumed whenever the DDR is in use, or is ready to be used, by the SoC. The Background Power only drops to the lower power down state after the work is done. The power state trace shows this transition from Active_standby to Precharged_power_down.
Figure 1: DDR Power State Trace
So how does Background Power consumption impact the energy efficiency of your SoC? The overall energy efficiency will depend on (a) the execution time of the application workload and (b) how quickly the DDR can complete its work and reach the more efficient shutdown state for the background power. The chart below shows the results for different memory subsystem configurations.
Figure 2: DDR Power Consumption
By using the DDR power model in Platform Architect MCO, we can analyze the impact of the DDR memory controller address mapping on power consumption and energy efficiency, specifically looking at the different location options for the Bank Address bits.
What do we see? For this application, DDR Background Power is a dominant factor. Finishing the scenario earlier, with Bank Address bits set to 14/15, gives an over-proportional energy gain. Compared to the worst case (at the bottom), the best mapping has the lower energy consumption. On the other hand, the best mapping has the higher power dissipation. This is the result of doing more useful work in a shorter period of time, due to the more efficient address mapping by the memory controller.
So what’s the right solution for your SoC? Find out by giving your DDR a Background (Power) Check!
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.