A View from the Top: A Virtual Prototyping Blog


Exploring the Benefits of a Hybrid Prototype

This month Nithya asked me to contribute a post on hybrid prototyping and add some color to how design teams have been benefitting from integration between virtual and FPGA-based prototypes. It’s been about six months since Synopsys announced the availability of a data exchange which links a Virtualizer Development Kit (VDK) to the HAPS FPGA-based prototyping system based on AMBA transactors and the HAPS UMRBus interface kit. Since that time we have further validated popular use scenarios for a hybrid prototype. So, what are the cases where there’s a benefit to connecting a SystemC TLM based model to an FPGA-based prototype?

These two approaches to prototyping seem well separated in a SoC design’s project schedule. Since there’s no dependency on RTL, a VDK could be up and operational for software development in a matter of weeks versus the months typically required to create and obtain the RTL and IP required for synthesis and implementation into an FPGA. Bring up time is even shorter if you are able to leverage one of the pre-engineered VDKs offered by Synopsys. And if the VDK is serving as the software development platform then what more utility does the FPGA prototype provide beyond the RTL validation that a simulator or emulator can’t deliver as quickly?

What we now confirm with customers is that model availability of SystemC or HDL is not clear cut along schedule timelines and that some SoC block validations demand high fidelity or clock cycle accuracy that require real world I/O interfaces and hardware to prototype completely. The other common condition is the preponderance of legacy SoC blocks that will be reused from revision to revision of the SoC design. In these scenarios, there’s a desire to have the option to freely mix and integrate the RTL/IP with a SystemC model for the SoC prototype.

At a recent engagement we completed a hybrid prototype implementation that connects a virtual (SystemC TLM) embedded Cortex-A9 CPU, cache and memory to a physical camera module and display. An image processing engine was implemented in the FPGA resources of a HAPS-60 system with a camera and encoder modules attached as HAPS daughter boards. Interrupt and data transfers between the model domains were accomplished using GPIO and AMBA transactors. Transactors serve to abstract the interface into the familiar Read/Write/Interrupt commands and automatically reconcile the loosely-timed virtual model with the cycle accurate hardware. In the virtual domain, Linux OS and application software layers executed image encode/decode. This was a great example of the validation and software teams collaborating to leverage the best of both prototyping worlds by taking advantage of the high MIPS throughput of the virtual A9 along with test jigs, sensor array and display hardware adjacent to an FPGA for hosting legacy image pipeline logic. We call this application case “in-context” validation because of the way the processor subsystem wraps around the new RTL modules being validated using the OS/firmware stack.

Engineering managers have also observed that this ability to bridge the prototypes helps break down the traditional walls that exist between the software and hardware development organizations causing them to jointly address system flaws rather than depend on the software team at the end of the project to drop features or apply workarounds due to unexpected silicon limitations and bugs.

What does the future hold for hybrid prototypes and transactor technology?

We are already seeing other scenario implementations where the FPGA-based prototype is attached to a host workstation for data-streaming. A C++ based application generating test patterns for validation. Again a transactor library API delivers an easy way to exercise the prototype by using familiar AMBA bus protocol commands. In the future we will likely see improved cross-triggering of debug features so system events from one domain are detected by the other. This may cause the embedded logic analyzer of the FPGA to sample status registers based on a software breakpoint encountered by the virtual prototype.

Connectivity between virtual, FPGA-based, and emulation tools for ASIC and SoC verification and validation gives more flexibility to engineers to connect design blocks that are most readily available and leverage the unique strengths of each prototyping system.

Troy Scott

Product Marketing Manager

FPGA Based Prototyping Software

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