Posted by frank schirrmeister on June 7, 2011
The Mentor ESL panel took place in its 9th year on DAC Tuesday in front of a very big “free-lunch-audience”. Wally Rhines kicked off the event in his usual data-driven manner, identifying the three types of design disciplines encompassing the SoC Design process: First there are “Hardware Custom IP Designers” challenged to shorten IP development and verification lead times. Second there are “Software Developers” who need to reduce software development, optimization and verification lead times. The third group are “SoC Architects and Integrators” who are challenged to design the full SoC for performance, low power and scalability.
The next generation design challenges for ESL – the drivers – are multicore design requiring virtual prototyping, system power implications and constraints requiring more than just power optimization and verification re-use throughout the flow from TLM to RTL requiring more automation and efficiency.
Turning over a new leaf, Mentor did invite a more management oriented panel from semiconductor (3), IP (1) and EDA (1) companies.
First on stage was Gadi Singer, Vice President at the Intel Architecture Group. He focused in his slides on HLS as a key step towards, but in his words called ESL three things – (1) necessary, (2) about time and (3) having not enough critical mass yet to become the next level of design entry. At Intel ESL is considered a long-term must have, it s being used for pre-silicon software development and post silicon readiness. There are several internal activities on HLS, but for broad deployment of HLS, several technical issues still need to be addressed. Among them are standards, improved ECO flows, better ESL model validation, formal equivalence capacity between TLM and RTL, SystemC linting and an effective integration between HLS written code and hand written RTL.
John Goodenough, Vice President of Design Technology and Automation at ARM talked about a “software first, sorry,hardware second” approach to ESL, somewhat apologetic towards the mostly hardware oriented audience. He mentiones several use cases including apps development pre and post silicon, architecture exploration, SoC design and validation and of course pre-silicon software bring up. Interoperability is crucial for ARM, SystemC offers some good starting points, but John also pointed out the still existing dilemma of running fast enough while providing enough accuracy on bus transactions.
Next up was Ken Hansen, Sr. Fellow, Vice president end Chief Technology Officer at Freescale Semiconductor. He talked about Freescale’s efforts to improve product differentiation with architecture optimization, software bring-up on virtual prototypes and co-design of hardware and software. As challenges to broader adoption he identified model availability and modeling expense, together with tool cost both for software developers and traditional EDA hardware users. He also commented on technical issues required for further proliferation, including better power modeling, automation of back annotation from implementation data and more seamless flows between virtual and hardware execution.
Jean-Marc Chateau, Director of System Platforms and Tools at STMicroelectronics, briefly reviewed the history of ESL adoption in ST since 2002 starting with C based hardware verification before IP RTL is frozen to pre-RTL software testing and debug for subsystems in 2008 to full pre-silicon software availability since 2011. As next frontier he sees specification level models, methodologies and standards.
Representing the EDA Industry, Simon Bloch, Vice President and General Manager, ESL/HDL Design and Synthesis Division at Mentor Graphics described TLM level flows from modeling of blocks to assembly, virtual prototyping, debug and optimization and then finally re-use of TLM models both for HLS implementation and hardware verification. Simon identified software validation as leading ESL driver from Mentor’s survey, followed by faster verification for fewer bugs and faster time to verified RTL (see graph on the left).
In the subsequent discussion moderated by Wally, all panelists seemed to be quite optimistic about actual ESL adoption. Especially virtual prototyping for software development got high marks from Intel, Freescale and ST. High-Level Synthesis also enjoys quite some attention. ARM identified model speed as basic issue for lack of deployment in software development, closely followed by cost. There was quite some discussion about the cost of the model development and who can actually do the modeling. Intel, Freescale and ST seem to employ specialists team to do the modeling for both internal and external use.
Overall, as concluded by Wally, management – at least on this panel – does not seem to be the problem for ESL adoption.
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.