Posted by frank schirrmeister on February 23, 2011
A trip up to Mount Tamalpais can not only be fun, it can change perspectives. It did hit me again when enjoying the panoramic view from up there, that system-level design value is hard to articulate. When taking the “View from the Top” perspective, one is so far away from the actual design implementation that value is pretty straightforward to understand but hard to translate into actual dollars. That is indeed a challenge we find in electronic system-level design as well.
The bay area is certainly created in a quite stunning fashion, I am enclosing the picture above as proof. I have used the analogy of “world design” to explain system-level design before, so this was living proof.
Our day up there was meant to take our minds off the house re-modeling, specifically the issues with the floor and ceiling height in the to-be-remodeled family room. On the architectural plan everything looked straight forward. Quite a contrast now while we are in implementation. The dry-wall is off, a fact that causes immediate regret given the bad shape the ceiling beams. Not to mention the floor height being off by an inch and the ceiling height changing between the kitchen and the family room.
No problem, says my contractor. Well, good for him. At this point I really have only limited options to proceed. Stopping the project is not really an option, so I will pay the additional amount in tools and work to get it done.
It all sounds so familiar from being in system-level design for as long as I have. And yes, I will get in trouble for having had work-thoughts on this trip to Mount Tamalpais. When a design team is 2 weeks prior to tape out, they will probably put up the money for additional resources and tools to achieve timing closure, the last ECO etc. In the backend of chip design the proximity to tape out is so close to what the designer is doing, that the value of adding resources and tools is obvious. Unfortunately for us in system-level design, the value gets harder to explain the farther one is away from tape out. The same guy putting up the licenses to close on timing two weeks prior to tape out, is typically much harder to convince 2 years in advance to tape out to spend money on system-level tools.
On the software side we have done a better job articulating the value of parallelizing software and hardware development. On the pure hardware side it may turn out that the only way to get over this issue to get closer to implementation. That does not necessarily mean that everything has to be automatically created from early system-level descriptions, but the predictability and correlation of early results with the implementation details will have to increase. This means the loop of abstracting and characterizing data from the actual technology implementation will widen even more. We have seen first cases of that in last years System-Level Reference Flow 11 for TSMC, in which implementation details from the implementation technology have been abstracted all the way up to the system-level.
Back to our home re-model here – there was no way for the architect to know how the beams in the ceiling looked like. He worked under the assumption that everything had done up to code, which is the equivalent of relying on implementation details being done the right way. Sometimes double-checking and confirming can help tremendously …
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.