A View from the Top: A Virtual Prototyping Blog

Archive for 2011

 

Increase the Battery Mileage with Virtual Prototypes

With this post, I would like to continue the topic of my earlier post “Can we stop power-hungry bugs from clawing their way through application software stacks?” In my previous post, I wrote about the difficulties software developers face with writing battery friendly software. I indicated that virtual prototypes (VPs) can address many of those challenges by providing visibility into the energy consumption of the software under development. Now, I would like to shed some light on how virtual prototypes can accomplish this.

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Can we stop power-hungry bugs from clawing their way through application software stacks?

Identifying and describing power issues is tough, let alone trying to solve them. “Power” issues can be very diverse. It’s even more difficult to explain how virtual prototypes can help to analyze “power” consumption. We often approach it by introducing how power information can be reflected in virtual prototype models, but there are many different goals and conflicting views on accuracy, granularity, modeling approach, data sources, etc.

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Early Software Development And The Supply Chain

Virtual prototypes are essential to effectively debugging a system and still meeting market windows.

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VP Software Debugging: Myths And Facts

In my last post I introduced the debugging challenges during porting, or developing native code, for Android.  This time I would like to outline how virtual prototypes can enable  software debugging and perform in an even better way. Before I describe what “better” refers to exactly, I want to shed some light on some prominent myths around the value of VPs for debugging.

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21 steps to setup a debugger for Android

Using the Google Search Debugger

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Good Reasons to Drop Old Habits? Change is Hard!

I am involved in discussions about adoption of system-level technologies a lot. System-level design in EDA and embedded software are always intertwined as the software is the main factor changing when going beyond RTL. Given that system-level design technologies expand beyond the traditional realm of hardware, their adoption is non-trivial for project teams. The overall situation reminds me more and more of Malcolm Gladwell’s “Outliers”: for success several factors have to fall in place together, not all of them in our control.

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How Many Apps Platforms Can a User Handle?

What do the Inchron Real Time Congress this week and my last weekend home project have in common? They both are all about complexity, real-time, apps and platforms those apps run on. In automotive and consumer domains, apps are running on platforms in systems of systems. The question to me at this point is how many platforms – like AUTOSAR, GENIVI, Android, IOS, Windows Mobile etc. – as well as versions of them can an apps interested user really handle?

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Who Knows System-Level Design Best?

Earlier this week I had the pleasure attending the Freescale Technology Forum (FTF). I was there to present on the Synopsys AUTOSAR activities, but was able to get a front row seat during Rich Beyer’s key note. I must say, the first FTF key note back as a public company after their IPO in may, left me nothing less but impressed. It also made me think about who really owns the system-level knowledge these days.

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Ethernet and Fault Tolerance in Automotive Systems

As a follow up to the DAC workshop called “Intra and Inter-Vehicle Networking in Automotive: Past, Present, and Future”, fellow Blogger Karen Bartelson and I had the pleasure of talking to Wilfired Steiner, Senior Research Engineer from TTTEch, about the challenges of the design of fault tolerant systems.

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Management Apparently not a problem for ESL Adoption

The Mentor ESL panel took place in its 9th year on DAC Tuesday in front of a very big “free-lunch-audience”. Wally Rhines kicked off the event in his usual data-driven manner, identifying the three types of design disciplines encompassing the SoC Design process: First there are “Hardware Custom IP Designers” challenged to shorten IP development and verification lead times. Second there are “Software Developers” who need to reduce software development, optimization and verification lead times. The third group are “SoC Architects and Integrators” who are challenged to design the full SoC for performance, low power and scalability.

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