Posted by frank schirrmeister on September 15, 2010
Now that I am back from honeymoon, the obligatory post-honeymoon-email-catch-up-marathon and then some business travel, I find myself in lots of discussions around application domains and the specific characteristics how system integrators, chip vendors and software vendors interact. How can one visualize the interaction between the different participants in the design chain? Is it applications driving the hardware or hardware enabling applications?
One way to illustrate design chain interactions are the “ASV Triangles”, which Alberto Sangiovanni-Vincentelli created in the late 90’s while I was product manager in the Felix/VCC team. Cadence VCC of course is described in “A Prescription for Electronic System Level Methodology” as one of the “Trailblazer Projects” for system-level design (Synopsys Behavioral Compiler being the other).
I remember seeing the original triangles sometime in 1999. The transition to platform based design was in full swing with platforms like Texas Instruments OMAP, Philips/NXPs nExperia and ST Microelectronics Nomadik under development. A hardware platform would be equipped with software APIs to allow application development to be relatively independent from hardware. This way video decoding was for example provided as a software API about which the application developer would have not to worry anymore. At the next revision the hardware provided underneath could change and as long as the API remained the same, application software would be compatible. This is illustrated with the upper set of triangles in the graph on the left. A range of applications can be mapped to hardware platforms with software APIs. Underneath different hardware architectures within a platform family support the applications.
This is where application specificity comes in because different application domains are driven by different requirements. The ITRS differentiates various product classes and design styles. They are SoCs, MPUs, Mixed Signal and Embedded Memory, with Networking, Consumer Portable and Consumer Stationary as sub-categories of SoC. In terms of driving markets the ITRS differentiates between Portable/consumer, Medical, Networking and Communications, Defense, Office and Automotive. In Networking for example it is all about increasing processing performance at constant die area, while in SoC Consumer Portable die size is actually shrinking and low power is the biggest issue.
As a result the ASV Triangles can now – roughly a decade later – be adjusted as I suggested in the lower portion of the graph on the left. The hardware platforms have become more programmable with multiple cores and software distributed among them driving the applications. The next step is to find application specific programming models which can be mapped from pure application design into programmable hardware architecture. This is what I would consider application driven design, in which hardware architectures enable different types of applications. Grant Martin and I wrote an article back in 2002 about the design chain effects called “A Design Chain for Embedded Systems”
Are we there yet? No. The time constants in the design world are pretty long and we are just now approaching mainstream adoption of the automation from the C-Level to hardware implementation. Virtual prototypes and architecture design as it stands today enable software driven development today, but it is largely manual, i.e. hardware platforms are provided as virtual platforms and software is developed on them after architecture decisions are made.
The next step will be to automate the partitioning of software across multiple cores – for which virtual prototypes already greatly help the debugging aspects today. However, completely automating the software partitioning is still some time away, even though the industry has figured it out for specific niches like HPC with technologies like NVidia’s CUDA.
As always – I am looking forward to your comments. It’s fun to be here in EDA. Times of transition are always offering many opportunities!
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.