Posted by frank schirrmeister on June 14, 2010
Writing this Blog post feels like being Sally Bowles in the musical Cabaret when she sings “Maybe This Time”. Since at least ten years the industry has been looking at the annual Design Automation Conference (DAC) and thought it would be the beginning of an era of system design, only to then realize next DAC around that most system-level design technologies have not yet crossed the chasm. Something feels different this year around. Here are my top five reasons why this is the year of system-level design, in a Letterman count down style:
FIve: Technology consolidation has begun. Well, it has accelerated. What has happened over the last year is that Synopsys bought CoWare, VaST and Synfora – enhancing their technology arsenal for for algorithm design, ASIP processor design, high-level synthesis, architecture design and virtual prototyping. Cadence has bought Denali – trying to catch up somewhat to Synopsys’s position in IP. The way we look at system-level design involving Systems on Chip and Chips in Systems is fairly straightforward. Users need lots of blocks in their designs. They need to either be able to re-use them or make new onesfast. They then need to integrate them into one or multiple chips in the system, assess whether their connections are properly architected and provide prototypes of them as early as possible to provide links to embedded software development. This results in needs for IP and various views of it (including system-level models), needs for technology to create new and differentiating blocks fast, to efficiently integrate blocks and finally to provide prototypes for software development. With the accelerated consolidation of technologies it becomes easier to optimize flows across different technologies. See us at the Synopsys System-Level Booth to check out the technologies we have in this domain.
Four: Design Chain enablement becomes a key requirement. Pressure for enablement across the design chain has increased tremendously. In the chain from semiconductor IP providers, to semiconductor providers, to system houses and finally software developers we increasingly see the respective next element of the chain driving the previous one in supplying the right models. A great example are virtual platforms, which allow system houses and semiconductor providers to more efficiently interact. See our suite demos on virtual platforms to find out more.
Three: Standards enable interoperability. The standards-enabled ecosystem (see picture on the left) has grown tremendously since last year. Standards like Accellera’s IP-XACT and OSCI/IEEE SystemC TLM-2.0 enable a strong ecosystem which allows to make sure that system-level technologies can interoperate properly, allowing users to create repeatable flows. Check out our partners at the Synopsys Standards booth to see how SystemC TLM_2.0 enables interoperability.
Two: Links to Verification find adoption. Being on the move to higher levels of abstraction is now combined with strong links back into verification. A fair portion of the system-level design market has been “ESL Verification” for a while, i.e. connecting transaction-level models to verification. Over the last year we did see the trend continuing and more and more developers now make software part of their testbenches for hardware verification. Check out the paper we co-authored with Infineon called “High Speed Models for Automotive Microcontrollers: Verification of the TriCore AUDO FUTURE TC1797 Virtual Prototype”.
One: Foundries are starting to incorporate system-level flows. Not only links to verification but even links into semiconductor technology data find their adoption. Performance, Power and Area (PPA) data characterized at various technology nodes can now be made available to drive decisions at the system-level. For example, in the TSMC system-level reference flow we recently announced, users can see with data created using virtual platforms at the transaction-level how the software will impact power consumption at different technology nodes. Check out our system-level reference flow at the TSMC booth.
Time will tell when and how system-level design technologies will cross the chasm and find mainstream adoption, but in a Sally Bowles “Maybe This Time” fashion it certainly feels different this time around. See you in Anaheim!
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.