A View from the Top: A Virtual Prototyping Blog

 

Model-based design – making the stretch easier!

By Johannes Stahl

When Carver Mead and Lynn Conway published their famous statement about the ‘tall thin engineer’ in their book “Introduction to VLSI System Design” in the early 80ies, designs had about 5,000 gates. Their vision was to change VLSI design into a process, that was repeatable and also that designers could understand the entire process well enough to create chips starting with the knowledge of the design intent down to the final mask set. If we look into the reality 30 years later, the opposite has become true. The SoC design process has been decomposed into a number of major categories: System-level design, Software development, RTL design, RTL2GDSII, Design for Manufacturing with vastly different knowledge disciplines.

In this View From The Top we of course do not look down to DFM, so we are definitely not the prototype of that tall thin engineer. At best we can see that our end point from a hardware implementation perspective is RTL for implementation and some reference model or test vectors, we provide to the RTL designers.

So how should system-level tools support hardware implementation flows? First of all the role of system-level tools is to make sure that the design intent is completely specified and is validated in the system context. Second the tools should facilitate an easy way of getting to RTL.

How do system-level engineers know, if their specification of design intent is complete? The best way for them is to express their specification in a way that is intuitive, allow for reuse of their knowledge and manages complexity through encapsulation. This is the essence of model-based design. In the domain of communication systems design any algorithm designer today will start with a conceptual block diagram and for simulation use C-models to explore the overall system performance. Block diagram based tools with a large amount of proven models, such as SPW and System Studio, are the default way for design teams today.

Once designers have captured their system using this model-based approach, the complete power of the high-performance simulation tools for performance exploration, specifically going to the required fixed-point precision is at their disposal. At a minimum this model-based fixed-point specification is a reliable, easy to understand meet-in-the-middle reference for RTL designers and algorithm designers. However with the proven Synopsys tools for implementation, algorithm designers can take it one step further: They can either rely on proven DSP implementation building blocks, built-in C to RTL translation technology or high-level model-based synthesis using Synopsys’ Synphony to automatically create RTL which can go straight into RTL2GDSII flows. Hundreds of thousands gates blocks are being designed every day with these flows, retargeting from FPGA to SoC included.

The basic questions of how much implementation expertise and algorithm design engineer needs and how much domain expertise an RTL designer needs does not have a fixed answer. Design teams will always need to stretch to bridge the gap. Synopsys can help to make the stretch easier!

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