Posted by frank schirrmeister on May 26, 2010
Well, productivity is an interesting issue. While ghost writing an article earlier this month I reviewed the ITRS roadmap and its predictions. The ITRS states that in order to keep up with the increased complexity of electronic developments over the next ten years, automation needs to provide more than 26 fold improvement on the hardware side and almost 50-fold for software. That’s quite a challenge. That makes me wonder whether these types of productivity improvement have been seen anywhere before …
First of all, my own Blog productivity has been miserable. My last Blog post two month ago? Ouch. Sorry for that. My excuse: We were very busy with the integration of the various acquisitions we made. However, the discussion on design productivity makes me think back on the two most memorable EDA speeches I have heard. One was in 1997, Joe Costello was talking about “negative target fixation” as part of a seminar tour. Productivity and how Cadence addresses its improvement, was the topic of the rest of the speech. At the time I was an EDA user and the speech helped convince me to join EDA. The other speech was given by Aart De Geus at DATE, I think in 2000 or 2001. I vividly remember going home with the thought “now that the Genome is deciphered, the design productivity gap is the next big problem to figure out. Let’s get to it”. And we did! According to the ITRS since 2001 design productivity has been improved through automation more than 18-fold for hardware and it has more than doubled for software.
So what does this all mean for us in EDA? The main message ITRS gives us in 2009 remains: Cost (of design) is the greatest threat to continuation of the semiconductor roadmap. Without the productivity improvements provided by tools, development cost would simply explode. The graphic on the left tries to illustrate this and is based on ITRS data. The overall semiconductor development cost – hardware and software – is kept in check under $100M. In order for that to happen, certain productivity deltas have to be achieved. Over the next ten years – until 2011 – this will have to lead to an overall, cumulative 50 fold productivity improvement in software development and a 26 fold productivity improvement in hardware development.
50 fold productivity improvements are hard to imagine at first. For my planned house re-model taking about 50 days, the equivalent would be to do all of it in a day. The involved design technology improvements cited by the ITRS are the “Intelligent test bench”, a “Concurrent software compiler” helping to automate the partitioning across processor cores, “Heterogeneous massive parallel processing”, “Transactional Memory”, System-level Design Automation” and ultimately a “Executable specification”.
So are those productivity improvements even feasible?
A good reference comparison from manufacturing would be automotive. The first production Ford Model T was built in 1908 in Detroit. It did cost about $850. This being $17,000 in 2007 inflation-adjusted dollars makes this about the same price of a new Ford Focus. This is comparable to the consumer industry. For the same price or less, users are getting much more functionality in their devices like cell phones and compute devices. Production time wise the first Model Ts rolled off the band about every 12 hours in the early days, every 93 minutes in 1914, once per minute in 1920 and at its peak every 24 seconds. That’s a 1800 fold improvement in manufacturing productivity within a decade or so. The item difficult to gauge is the car development complexity. I did not find real data here, but GM introduced the first Engine Control Unit (ECU) with a microprocessor in 1979. Combine that with the fact that today’s cars easily have more than 50 ECUs in them, suddenly the factor 50 no longer looks that out of the question anymore.
At the end of the day the challenges for the next decade to achieve the required productivity improvements seem to be doable. Given the mix of hardware and software changes our increased attention here at Synopsys on software development certainly seems to be timely and correct.
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.