Pistols at Dawn: Finding the middle ground between building and assembling

Being challenged to a duel can be scary. It often helps to re-visit what one is dueling about. The discussion in question here is about the role of IP reuse vs. high-level synthesis. And as is most life situations the truth probably lies somewhere in the middle, and for sure not in the extreme position 🙂

What happened? In my last post I likened the Oakland harbor to a USB interface. Thomas Bollaert commented in his Blog entry title ‘The “S” in ASIC’ on the role of IP reuse and that ‘IP has an important role to play, but not an exclusive one’. Hey, I fully agree. How let’s look at where we are on the scale between IP reuse and creation of new IP.  I would at least want to augment the comment ‘it will be quite some time before chips are an assemblage of IP blocks’ with the notion that large chunks of design are already today. The graph on the left shows IP reuse data from Semico Research. The average number of IP blocks per chip is already around 50 and set to grow to more than 70 over the next couple of years. Together with data that more than 50% of a chip is reused today already (a number which is set to grow to at least 60% over the next couple of years), there is already a large amount of IP assembly going on today..

So what are these IP blocks? Well, processors like ARM, Atom, MIPS, PowerPC etc. for one. These blocks are designed to be a scalable business – i.e. being sold multiple times. The analogy of the Oakland harbor was meant to indicate other blocks which are a scalable business – connectivity blocks for defined interfaces like USB, SATA, DDR etc. Given that these follow defined standards, the main decision is whether to have them available or not. A custom implementation will in most cases not be differentiating for a chip vendor. As a result they will tend to reuse IP for those and focus their differentiation on some of the custom blocks Thomas describes (like video or audio) as well as on the software provided on the processor.

So with assembly of IP blocks being a given, where does high-level synthesis fit in? Well, it certainly does for new blocks. Even if IP-reuse grows to 60% or 70% as predicted, those remaining 30% are still a big chunk of work. That’s where high-level synthesis fits in with two effects. First, it accelerates the time to implementation. In addition it increases verification efficiency by enabling transaction-level verification combined with a repeatable, automated flow to implementation.

How far one takes this depends on perspective. Some vendors definitely take it a bit too far in questioning IP reuse at the RT-level as “high effort, error prone work” and “restricting architectural flexibility”. Pushing TLM models as the only golden source from which one synthesizes takes it too far. High-level synthesis from the transaction-level needs to be seen in conjunction with IP reuse of larger blocks like USB, SATA, DDR etc. Just like in the transition from gates to RTL, I doubt that high-level synthesis will eradicate reuse of smaller blocks. It will augment it and perhaps even use it by using the smaller blocks of IP to map to.

As always, the truth to me lies somewhere between the extreme positions.