Posted by frank schirrmeister on January 19, 2010
Commuting back home on Central Expressway, KFOG was playing Pink Floyd’s “The Wall”, which reminded me of all the comments that projects will run into brick walls if they do not adopt system-level technologies. As January is the month of predictions, let’s see whether the trends in semiconductor design can add more bricks to that wall into which projects allegedly will run into (picture source here).
As I wrote in my column in the 2010 Outlook issue of Electronic Design “2010 Will Change The Balance In Verification”, there are definitely some changes ahead in hardware verification, mostly caused by the increased importance of embedded software for the success of semiconductor designs. However, in looking at the trends in semiconductor design more holistically, there are eight trends which will add more bricks into the alleged complexity wall. Hey, and that in exchange will system-level design all the more necessary!
The eight major trends are (1) further miniaturization towards smaller technology nodes, (2) a decrease in overall design starts, (3) increased programmability and trends to software, (4) IP re-use, (5) application specificity, (6) adoption of multi-core architectures, (7) low power and (8) an increase of the analog/mixed signal portion of chips. All of these have profound impact on requirements for system-level design, specifically prototyping – using virtual platforms and FPGA prototyping:
Further miniaturization (1) increases the sheer complexity of things users have to deal with. Judging from “The magic number 7 plus minus 2” users can’t handle complexity without divide and conquer. From a prototyping perspective virtual and FPGA prototypes simply need more capacity to prototype designs. This is a great trend causing more desire to combine virtual and hardware prototypes.
The decrease in overall design starts (2) makes companies consider their investments much more carefully. As a result, platform based designs have emerged, which are flexible and programmable. In exchange this drives to more processor based design and more software. This increases the need for early software development in virtual platforms even prior to RTL and FPGA prototypes once RTL is available but still well before silicon.
Increased programmability (3) and the trend towards more software are again great for virtual platforms and FPGA prototyping. Getting to an executable of the hardware under development as early is possible is becoming even more crucial for early software development, verification and architectural exploration.
IP Re-use (4) is further increasing. Given that the integration of ten’s of IP components is not easy, delivery of transaction-level models in with SystemC TLM-2.0 APIs becomes mandatory for more and more customers. Great times for offerings in the transaction-level library space.
Application specificity (5) is a important trend enabling system-level design for algorithms and for processor design. For example, LTE and other application specific libraries enable model based development of algorithms as well as transaction-level models for processors define application spaces a tool can play in. This means great times for tools with the right application libraries.
Multicore architectures (6) may be the trend finally driving virtual platforms towards mainstream adoption. Good luck with trying to control multiple processors with breakpoints in the final hardware. System virtualization helps to allow multicore debugging, i.e. being able to individually control different processors flexibly to find race conditions, deadlocks etc.
Low power (7) requires users to make assessments – and changes – as early as possible in the design flow. Trying to optimize for low power at stable RTL is crucial but likely has much less impact than choosing the right split of processors and dedicated hardware accelerators at the architectural level in the first place. Great times for ESL low power analysis.
Higher analog/mixed signal content (8) leads to more specific needs to validate designs within their respective system contexts. Great times for prototypes – virtual and hardware – which can connect well to their respective system environments like USB, Ethernet and even wireless air interfaces.
So will 2010 be the year of ESL? As they say, predications are hard, especially about the future, but the various trends in semiconductor designs are definitely continuing to stack up bricks into those walls projects might run into if they do not employ system-level technologies. Interesting times!
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.