A View from the Top: A Virtual Prototyping Blog

Archive for 2009

 

ESV – A Megawatts perspective

Rajesh Gupta UCSD put it in clear words: “Low power design for complex chips is a solved issue. Designers have tools and methodologies and getting their job done.”  Game over?

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The “S” in ESL makes it difficult …

Just as the Design Automation Conference in San Francisco comes to a close some cynics are pointing out that once again this was the DAC of ESL and we probably can look forward to another one like that next year in Anaheim :(. This feels like the proverbial road trip during which you hear from the back seat every five minutes “Are we there yet?”. There certainly were interesting panels and events at DAC, like the System Prototyping panel yesterday, for which Rick Nelson wrote a good write up here.

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How will you deploy Electronic System Virtualization?

Today the problem for companies developing electronic systems is not anymore the existence of the right technology, but rather how will I deploy it. Electronic System Virtualization must cover areas such as processor design, system architecture, oftware development, go-to-market enablement, configuration, etc. The virtualization of the electronic system must start from the specification all the way to the deployment of the system itself independently of the system being a core, an SoC, a board, a device or a network of devices.

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46th DAC – Debating ESL, again…

For those tracking the history of the last 10 years of DAC panel discussions about ESL, they fall largely into two camps: the language debate and the high level synthesis debate. The 46th DAC was no exception to that pattern, and frankly, it is getting very old…

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Virtual Platform Workshop at DAC

Qualcomm reporting on the opportunities and challenges of Virtual Platforms for their system designs. QC has been highlighting the productivity gain they get from Virtual Platforms for Software Development, Architecture Definition, Hardware Development and Early Customer Success. Qualcomm is following an incremental Virtual Platform creation approach to incrementally enable software development and get value out of VPs as early as possible. QC has reported a significant quality gain because they are able to develop the tests upfront and do not need to wait until the HW is available for the test development. VPs help QC to improve the coverage of their testing using complex software use-caes. VPs have enabled QC to create tests that they could not create before. Challenges remain on the Virtual Platform enablement side. For QC it was key to choose a standards-based modeling language and TLM to ensure interoperability between models. The driver to select a tool and/or language is its ability to create virtual platform models that are fast, at a higher level of abstraction, are interoperable, and that can be created in an easy way. QC reported that it is key for them that their engineers are enabled to carry out the modeling. It is of significant importance that a wider set of engineers/IP architects are enabled to create models with the above mentioned characteristics.

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System Prototypes: Virtual, Hardware or Hybrid?

The Tuesday’s panel “System Prototypes: Virtual, Hardware or Hybrid” at DAC was well attended with an active and exciting discussion among the panelists and the audience. Panelists came from Amicus Wireless, Qualcomm, LSI, Synopsys, ST-Ericsson and CoWare. There was a consensus that there is no on-size-fits all solution for prototyping. Different design tasks such as system level architecture definition, software prototyping and bring up and implementation prototyping have different requirements on the prototyping solution. Qualcomm and ST-Ericsson have reported about their successful adoption of virtual prototyping using Virtual Platforms for early software development. Both reported that Virtual Platforms has significantly smoothed their software bring-up step-function that they typically had without Virtual Platforms and when the hardware became available late in the design. Questions have been raised about the accuracy of Virtual Platforms. Here, the panelists where in agreement that a Virtual Platform does need to provide the accuracy required for the different design tasks such as being just functional accurate for software development. I have been reporting a trend that we see at our Electronic System Virtualization solution users moving away from spreadsheets for the architecture definition. This was hitting a question from  the audience how Virtual Platforms can be used for HW/SW partitioning. System level architecture prototyping is done using non-functional workload models characterizing traffic scenarios for application/task mapping as well as interconnect and memory subsystem optimization. This way the dynamics of a system can be captured which is not possible using static spreadsheets. Other questions were about using Virtual Platforms after silicon is out. Here, the Google Android Emulator was mentioned as a perfect example how Virtual Platforms deliver value to even the application software developers by having access to a fully virtualized environment including GPS, Internet, Accelerometer to develop disruptive applications. People in the audience where also reporting about the trouble they face when trying to bring up systems on an FPGA, it simply does not fit for many cases. FPGAs are used for block level implementation prototyping but cannot provide a full environment. It was an exciting panel and it has clearly shown the increasing demand and adoption of Virtual Platforms in the industry.

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DAC Tuesday – Even more on System Design …

The votes were cast, THANK YOU for your votes to all of us EDA Bloggers and CONGRATULATIONS to Karen Bartleson for winning  the “NEXT EDA BLOGGER” contest.

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DAC: Electronic System Virtualization Success at Motorola

This week CoWare has been pleased to welcome Victor Leonov, distinguished member of technical staff, Motorola Mobile Devices and user of CoWare Platform Architect, to the CoWare DAC booth as a expert guest speaker on architecture design. His presentation, Achieving Optimal Cost-performance Balance in Advanced Wireless Modem Chipsets using Stochastic Simulation, was of high interest to SoC system architects and project managers here at the show.

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A rant: Will the agent of change for SW stand up?

 How many time have I heard now that software is the growing problem, that software is the savior for the traditional EDA companies, that the software teams are out growing the hardware team, yet the software tools budget are not, …

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The DAC of ESL (Again)

Well, on Gary Smith’s “What To See at DAC” list 16  out of 24 recommendations start with ESL. The most thoughtful comment I heard on ESL during yesterday’s DAC was related to ESL, but made me think. John Aynsley of Doulos said during the”Town Hall” meeting that he had thought that this years DAC would be the DAC of high-level verification, but it seems it is the DAC of high-level synthesis. Well, the two very likely are related. The drive towards higher levels of abstraction always had been driven by a combination of faster implementation and more productive verification – assuming you can be more productive “up there” and then minimize the verification overall as I outlined in a recent column called “When one plus one needs to be less than one”.

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