Posted by frank schirrmeister on October 12, 2009
We all make these decisions on a daily basis. For me it is about the morning coffee. Do I prepare it at home, get it as early as possible, or do I wait until I am passing the coffee shop on my way to work, a path I have to take anyway.
For model usage we are facing a similar issues. When looking at a standard design flow, it is a fairly straightforward decision to take RTL – something which will be created in a path of a project anyway – and use it to create with fairly predictable overhead a software development environment, may it be an FPGA prototype, an emulator or software based hardware/software co-verification. In contrast, the C models needed for virtual platforms – for example to feed into our Innovator based virtual platforms – are not part of most “normal project flows”, which today still start with written specifications and then lead into RTL.
Today we introduced the Synphony High-Level Synthesis solution, which takes M language input – often used interactively for algorithm analysis – and creates RTL from it. Together with M, Synphony HLS accepts model-based design entry. Examples for model-based design entry here are The Mathworks Simulink and of course our Synopsys System Studio.
When looking at M at first I myself was quite confused, as it is often used interactively for algorithm analysis. However, by itself there is really not much simulation there. However, we used the opportunity of our LTE Whitepaper about next generation wireless systems to query users on which tools they use for algorithm design entry. Interesting enough, as the graph above shows, out of more than 500 respondents, 32% pointed to M, 29% pointed to C based entry and 22% to model-based design entry, with our Synopsys System Studio fairing very well as number two used tool (32%).
M is really the next level up above C based technologies – and therefore Synphony HLS is really complementing C based synthesis technologies. Looping back to my coffee analogy earlier, one key item I am excited about is the Synphony High-Level Synthesis capability to provide on the way to implementation models which can be used for virtual platforms and verification. In an example we are showing to customers, 3 lines of M translate to 20 lines of C-code and 200 lines of RTL. As a result, creating C models as natural byproduct of this flow, will be yet another source of models for virtual platforms, in this case covering the communications and multimedia application domains.
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.