A View from the Top: A Virtual Prototyping Blog


Riding the Software Hockey Stick

TrendToSoftware Well, for those of you familiar with dancing, I am not talking here about the sequence in Rumba – albeit that’s fun too – but instead of being within a hockey stick adoption curve. How do you identify a trend clearly? You ask the same question multiple times and over time you will see the trend. That’s what we did with the following question: “What percentage of your total project effort is spent on software development (vs. hardware development) during design?”. We asked this question since March 2008 – at the Synopsys North American User Group meeting SNUG, then throughout the year during later user group meetings. We then asked again at DVCON 2009 in San Jose and finally at two recent events – the Virtual Multicore Conference and the EETimes Virtual SoC Conference (for which by the way you can still register and watch the archived presentations and our virtual booth).

The result is quite amazing to me and shown in an animated graphic on the left. Essentially, over this 18 month period the answer to this question shifted fundamentally. At SNUG 2008 84% of the users responded with either “0% to 25%” or “26% to 50%”. That means that for 84% the hardware effort was dominant. However, 46% already responded at that time that the software effort is between “26% and 50%”. I was quite happy with that response at the time.

Well, over the last 18 month the answer has shifted quite fundamentally. As the animation shows the numbers for software increased over the year. 15 month later, at the Virtual Multicore Conference, 61% of the respondents reported higher effort on the software side. And most recently, 18 month after we asked that question for the first time, at the EETimes Virtual SoC Conference 54% reported higher effort on the software side. That number is slightly down from the previous peak, but the audience was much more hardware oriented compared to the multicore conference.

So what does it all mean? Are we within the hockey stick transition to software taking over in importance in chip design? Perhaps. This is a good and relevant data point. And the impact on traditional hardware techniques may be even more profound, as I outlined in my Electronic Design column “When One Plus One Has To Be Less Than One”. Software becomes the means for verification, i.e. the software running on processors in the design becomes the actual testbench. The main advantage here is that the testbench can be re-used across different process steps:

  • Verification can start using transaction-level models and virtual platforms even before RTL is available
  • Once RTL is developed, the same testbenches can be re-used, now verifying the RTL in co-simulations of TLM models and RTL
  • When the RTL is mapped to a FPGA prototype, the same testbench can still be re-used – both in pure FPGA hardware and in System Prototypes – hybrids of virtual platforms and FPGA prototypes.
  • Even post silicon the same testbenches can be executed to test that that actual silicon is correct.

There are obvious differences in the amount of verifiable detail in each steps. Still, it looks like we have interesting times for verification ahead of us.

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