A View from the Top: A Virtual Prototyping Blog


The “S” in ESL makes it difficult …

Just as the Design Automation Conference in San Francisco comes to a close some cynics are pointing out that once again this was the DAC of ESL and we probably can look forward to another one like that next year in Anaheim :(. This feels like the proverbial road trip during which you hear from the back seat every five minutes “Are we there yet?”. There certainly were interesting panels and events at DAC, like the System Prototyping panel yesterday, for which Rick Nelson wrote a good write up here.

image Personally I attended the 7th Annual ESL Symposium Luncheon sponsored by Mentor Graphics and moderated by Wally Rhines. The panelists included Nitin Chawla from ST, Joachim Kunkel from Synopsys, David Black from ExtremeEDA and Wolfgang Rosenstiehl from the University of Tuebingen and Alan Su from GUC.

As always Wally had lots of data. While he likened ESL at the beginning to technologies which took 30 years to adopt, he then showed graphics like the one on the left  confirming actual market growth. He called ESL one of two technologies leading growth in EDA. According to Mentor’s surveys, ESL adoption is driven by design complexity, verification challenges, design challenges to meet power and performance requirements and time to market demands.  When it came to the panelists, Joachim Kunkel and Alan Su focused in their introductions on system prototyping while the other panelists were more focused on high-level synthesis.

At one point the panelists had gone down the route of ESL synthesis so far that Daniel Gajski stood up and asked the panel whether ESL is only high level synthesis or whether there is more to it. The panelists attempted answers, mixing in verification, but in my mind one key question was left unanswered: Where does a block and where does a system start? What is the “S” in ESL?

Unfortunately the discussion seemed at times to miss the separation of block development and block integration. High-level synthesis is today well applicable for block development. However, with block re-use in hardware reaching 70% and 80% levels, the other challenge in the design process has become the integration of blocks, re-used or newly created. Several questions later-on confirmed this lack of clarity as the question “how far away are we from synthesizing complete chips” came up in several variations.

Overall, however, I am glad that according to the data ESL is growing and has not been voted of the EDA island … Off to the next round and let’s hope that we are progressing even further until we meet in Anaheim next year.

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