Posted by Johannes Stahl on July 30, 2009
Rajesh Gupta UCSD put it in clear words: “Low power design for complex chips is a solved issue. Designers have tools and methodologies and getting their job done.” Game over?
Not really, as debated by the panelists during the Design Automation Conference panel on “From Milliwatts to Megawatts”. While some of the panelists were still hanging on to do better RTL implementation – albeit making use of more sophisticated approaches with high level synthesis – Nokia and IBM had a much different perspective. Power is a system issue and much of it is determined in how the software stack enables the user to get the most value from the application within the power budget.
On one end of the spectrum is getting the best response time in a data center running expensive Oracle software. Shutting down as many servers as possible within the performance requirements is the answer according to the IBM fellow.
One the other end is managing a smart phone running running out of juice while navigating using Google maps. Does the phone shut down the music player automatically or does it give the user an option to chose how long the battery will still last; the challenge presented by the Nokia Berkeley research lead.
The architectures to deliver on low power will vary a lot. Essential is that only a systemic view using the software application use cases provides the answer for defining the system architecture and the power management strategy implemented in software. The answer is Electronic System Virtualization, not behavioral hardware synthesis.
Will the 47th DAC next year have a panel on real cases of power optimization at the software level?
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.