A View from the Top: A Virtual Prototyping Blog


The DAC of ESL (Again)

IMG00337 Well, on Gary Smith’s “What To See at DAC” list 16  out of 24 recommendations start with ESL. The most thoughtful comment I heard on ESL during yesterday’s DAC was related to ESL, but made me think. John Aynsley of Doulos said during the”Town Hall” meeting that he had thought that this years DAC would be the DAC of high-level verification, but it seems it is the DAC of high-level synthesis. Well, the two very likely are related. The drive towards higher levels of abstraction always had been driven by a combination of faster implementation and more productive verification – assuming you can be more productive “up there” and then minimize the verification overall as I outlined in a recent column called “When one plus one needs to be less than one”.

Most of the day I was actually tied up in customer meetings. I heard good things about our System Prototyping Luncheon with LSI and Intel as customer presenters with more than 100 attendees. In our System-Level Catalyst area at the Standards Booth we had standing room presentation (see picture) and demos. So users are definitely interested in understanding ESL technologies.

I briefly attended the town hall meeting at the SystemC North America User Group. They employed interesting technology with which the audience could immediately vote on questions of interest (TED alert – in Germany 15 years ago we had this thing called TED for which you could call in a vote … sometimes with interesting results 🙂 ).

Results were sometimes interesting albeit not always surprising. 90% of attendees liked an open source reference simulator implementation. The majority of attendees seemed to use SystemC for modeling at the Loosely TImed level of abstraction. An automatic path to implementation was the most requested “What does SystemC need”.

At DAC today? There is GreenSocs Breakfast Panel titled: “SystemC TLM: Just add water?” at 8:30 am. You can expect lively discussions when Synopsys’ Andrew Dauman participates in the panel “System Prototypes:Virtual, Hardware or Hybrid?” at 10:30 am and Joachim Kunkel discusses “Silicon IP – Beyond Chips to System” at 3:30 pm. At our Standard’s booth we will have today the following schedule:

Time Demo Pod Theatre
9:00am-10:00am Synopsys  
10:00am-12:00pm SDV  
11:30am   Carbon Design Systems, “Addressing the Model Needs of the Virtual Platform Cycle”,

Bill Neifert

12:00pm   SDV, “Bridging Abstraction Levels Between Transaction and Signal Level”, Bernard Deadman
12:00pm-2:00pm Carbon  
12:30pm   CoFluent, “Automatic generation of SystemC IPs & use cases for Innovator from CoFluent Studio “

Jerome Lemaitre, Solution Specialist

2:00pm-4:00pm ChipVision  
3:30pm   CoWare, “SystemC Standards Interoperability with CoWare: Get Value from Using–not Building–a Virtual Platform”, Tom De Schutter
4:00pm -6:00om CoWare  

See you on the show floor!

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS