A View from the Top: A Virtual Prototyping Blog

 

Don’t Retract My Math Grades Please …

Getting of the campaign trail here for a bit – if you have not yet voted for me as EDA Top Blogger, please do so – I reviewed some statistics which went into an article I recently wrote for my ED Column. The article is called ‘When One Plus One Has To Be Less Than One” and I am seriously expecting to get in trouble with my math teacher back in Germany.

Sorry, Herr Stabba, I know that 1+1 can not be smaller than one, but that’s actually what we are asked to do here in EDA. Exciting – a new attempt at the impossible every day … 🙂

What I argued in the article was essentially, that every new methodology has to have a good, measurable ROI. With moving to a next level of abstraction, the additional work spent there has to pay off, i.e. the new tasks added on, have to lead to less work overall. Specifically, when using higher levels of abstraction for verification, the approach can only be adopted if overall the verification effort gets reduced.

In the article I do refer to some statistics we measured here at Synopsys, and given that the upcoming theme for our virtual platforms at DAC will actually be “Software Driven Verification”, I wanted to detail them a little bit:

Well, there is hope yet. To my surprise, in a recent survey we did at DVCon, over 50% of the respondents told us that they are already running embedded software on embedded processors in their design to verify the surrounding hardware. We also know that simulation of RTL in conjunction with TLM processor models runs between 20 to 50 times faster than their pure-RTL counterparts.

imageSo let’s be a bit more specific. We actually asked the question twice now … at DVCon009 in February and at Virtual Multicore Conference in June. We got 54 respondents at DVCon and 171 at the Virtual Multicore Conference.

The results are shown on the left here and averaged over the two events. The results were remarkably similar for both events.

First, only 10% of the designs given this audience have no embedded processors in them. 90% of the designs with processors. The second item then was surprising. We specifically asked: “Are you using the processors in your design for hardware verification, i.e. run test benches on them to verify hardware?”. More than 50% responded with yes, some of them only use this approach for post silicon validation. While I had seen this use case in customers, I was surprised by the overall percentage of respondents here.

So here we go. This may just be a pivotal point for hardware verification … using the embedded software to do it. There are lots of advantages:

  • Users can start with the test bench development on TLM processor models prior to the actual availability of RTL
  • Once RTL is available, TLM models of the processor can be used to speed up verification, keeping as much at the TLM level as possible
  • When a rapid prototypes becomes available with RTL getting stable, processor models can still remain on the TLM side in the virtual portion of System Prototypes.
  • Once Silicon becomes available, the same test benches still run.

True verification re-use across the different stages. Sweet.

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