A View from the Top: A Virtual Prototyping Blog

 

Viewing DAC From The Top, Partying and Voting …

There are lots of system-design activities going on at this year’s DAC in San Francisco. July 26th to 31st. Here is the list of events I’ll be looking at and you can expect some Blog entries from those events as well.

But first, given that I just came back from a great 4th of July weekend, please excuse my mindset and let’s start with the partying. 🙂 The Denali party happens on Tuesday night, July 28th, at 8:00 pm at the Ruby Skye. My Blog has been selected as one of the eight finalists in the EDA’s Next Top Blogger contest. So please vote for my Blog, I am the second one from the left in the bottom row, yes, the one holding up his head. OK, now that I have that off my chest, here are the things I’ll be looking at (other than partying):

On Sunday evening I will attend the traditional DAC kick off with the DAC Welcome Reception from 5:30 pm to 7:30 pm in the Grand Ballroom of the Intercontinental Hotel, sponsored by EDAC. With presentations from Wally Rhines and Gary Smith high entertainment value and lots of system-design messaging is pretty much guaranteed.

Once per day I will be in our demo suite at the Synopsys Booth 1120 talking about how software driven verification improves your overall productivity, shaving months off your product schedules. You can register in advance for a demonstration. Look for the session titled “Virtual Platforms: Increasing Productivity using Software Driven Verification”. In addition to the demo suites, I will also present ways to increase verification productivity on Wednesday, July 29th at 3pm at the DAC Exhibitor Forum.

My colleague Filip Thoen will show Synopsys SuperSpeed USB 3.0 virtual platforms at the DAC Virtual Platform Workshop (sign-up required), also on Wednesday, July 29th. A virtual platform workshop at DAC? You read right. Software and system-design seem to become mainstream at this traditionally hardware focused event.

In addition I invite you to experience SystemC based interoperability at our Standards Booth 1016 when some of our System-Level Catalyst Members – ARM, Carbon,  CebaTech, ChipVision, CoFluent, CoWare, Doulos, Forte, GreenSocs, Imperas,  JEDA, SDV and Target Compilers – present their solutions focused on System-Level ecosystem. See below for the detailed schedule.

Additional Synopsys supported events focused on System Prototyping, SystemC and interoperability are the System Prototyping Luncheon on Monday July 27th at 11:30 am, the North American SystemC User Group on Monday, July 27th at 1:30 pm and the GreenSocs Breakfast Panel titled: SystemC TLM: Just add water? on Tuesday, July 28th at 8:30 am.

Finally, you can expect lively discussions when Synopsys’ Andrew Dauman participates in the panel “System Prototypes:Virtual, Hardware or Hybrid?” on Tuesday, July 28th at 10:30 am and Joachim Kunkel discusses “Silicon IP – Beyond Chips to System” on Tuesday, July 28th at 3:30 pm.

See you in San Francisco!

System-Level Catalyst Members in the Standards Booth (# 1016)

System-Level
Catalyst Member
Booth Demo Time Booth Presentation Time
ARM Wed 7/29 1:00pm to 3:00pm Wed 7/29 3:00pm to 3:30pm
Carbon Tue 7/28 12:00pm – 2:00 pm Tue 7/28 11:30 am – 12:00 pm
CebaTech Mon 7/27 12:00pm – 2:00 pm Mon 7/27 11:30 am – 12:00 pm
ChipVision Tue 7/28 2:00 pm – 4:00 pm Tue 7/28 4:00 pm – 4:30 pm
CoFluent Thu 7/30 9:00 am – 11:00 am Tue 7/28 12:30pm to 1:00pm
CoWare Tue 7/28 4:00 pm – 6:00 pm Tue 7/28 3:30 pm – 4:00 pm
Doulos Mon 7/27 4:00 pm – 6:00 pm and
Thu 7/30 11:00 am – 1:00 pm
Forte Wed 7/29 11:00 am – 1:00 pm
GreenSocs Wed 7/29 9:00 am – 11:00 am Wed 7/29 10:00 am – 10:30 am
Imperas Mon 7/27 2:00 pm – 4:00 pm Mon 7/27 4:00 pm – 4:30 pm
JEDA Mon 7/27 10:00 am – 12:00 pm Mon 7/27 10:30 pm – 11:00 pm
SDV Tue 7/28 10:00 am – 12:00 pm Tue 7/28 12:00 – 12:30 pm
Target Complier Wed 7/29 3:00 pm – 5:00 pm Wed 7/29 2:30 pm – 3:00 pm

Times subject to change – Please check-in at the Standards Booth at DAC for a final schedule.

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