A View from the Top: A Virtual Prototyping Blog


Hammers, Nails and the Spirits That I Called …

Und sie laufen! Nass und nässer               – And they’re running! Wet and wetter

wird’s im Saal und auf den Stufen, – get the stairs, the rooms, the hall!

Welch entsetzliches Gewässer! – What a deluge! What a flood!

Herr und Meister, hör’ mich rufen!   –   Lord and master, hear my call!

Ach, da kommt der Meister!   –   Ah, here comes the master!

Herr, die Not ist groß!   –   I have need of Thee!

Die ich rief, die Geister,   –   from the spirits that I called

werd’ ich nun nicht los.   –   Sir, deliver me!

From “Der Zauberlehrling”, Johann Wolfgang von Goethe, Translation by Brigitte Dubiel

Goethe's ZauberlehrlingWell, there is this moment in blogging when you review your post and your finger hesitates for a moment before clicking the submit button. When I wrote my last post there was, as always, that moment. And I actually did think of a valued colleague over at Cadence and how he would react.

I did not think that I would unleash – between us Trekkies – the “Wrath of Ran” :).

Punctually for halloween I now finally understand how the sourcerer’s apprentice in Goethe’s “Zauberlehrling” feels like (I took the picture from here). There is the famous line every German knows and cites: “Die ich rief die Geister werd’ ich nun nicht los”, “from the spirits that I called, Sir deliver me!”. In Goethe’s poem the apprentice unleashed something small and it got out of hand.

Well, that’s how I feel.

And before I move on and leave this overall topic and exchange of posts, let me state for the records that there was no intent in my last post to position any solution as the “universal” solution to early low power analysis. Also, for the record, I do respect Ran at Cadence as professional and colleague – we worked for a long time together. There was no personal attack intended here. I merely was admiring the elegant writing and mixing of two product offerings in a press release.

When discussing this matter with a friend, he pointed out rightfully so that both Ran’s and my post suffer from “Hammer and Nail-itis”. In fact, he pointed out, the combination of Cadence’s estimators (InCyte), C based synthesis, Palladium, and Synopsys virtual would be pretty powerful!It’s a good thing then that we acquired Synplicity which brought us Synplify high-level synthesis and Confirma FPGA Prototyping to Synopsys, and of course, that we have existing interfaces between our Virtual Platforms and Eve’s solutions.

So it looks like we all agree on a couple of things, especially that power analysis as early as possible is very important.

The flow Cadence suggests works pretty well and I have seen it at users being used. One remaining issue is how well the synthesized results correlate to the actual implementation later. I had analyzed this together with Eike Schmidt when we both were at ChipVision in a paper called “Towards Activity Based System Level Power Estimation” at the IP/SoC conference 2005. The energy consumption can be quite different based on the chosen micro-architecture during high level synthesis and even based on the stimulus.

Power trade-offs in a JPEG Decoder based on stimulusThis figure shows the deviation of energy consumption due to different input stimuli for a JPEG decoder created using high-level synthesis. Each column represents an RT architecture optimized to minimize the energy consumption when decoding the depicted data. The rows stand for the data used for estimating the power of that respective architecture. Results are given separately for logic and memory. The diagonal shows the relative energy consumption compared to the reference picture “White Noise”. The percentages in each column are measured relative to the column architecture as reference. An increase of up to 63% in energy consumption can be observed when operating the design (optimized for “constant grey) with different data then originally optimized for (“white noise”).

For architectural exploration of hardware blocks the suggest flow is a great flow. Too bad, that the original press release actually did not mention high-level synthesis at all 🙂
It remains the software side and the estimation of power caused by software.

It is not my place to dispel the misperceptions of virtual platforms articulated in Ran’s post. There are much better sources, like Bill Murray’s excellent article called “Virtual platforms – a reality check Part 1 and Part2”, the words of Texas Instruments and – sorry, Ran, I cannot resist – the words of Freescale, Cadence and Synopsys (Virtio) in “Parallel Software Development with Emulation and Simulation Tools for Mobile Extreme Convergence (MXC) Architectures”.Suffice it to say, virtual platforms do not take 9-12 month to develop, especially since SystemC TLM-2.0 APIs and our DesignWare System-Level Library make 100s of models available in a interoperable fashion.

On the contrary, today we are working with customers in projects for which the virtual platform is available for software development 8 month prior to RTL. And the accuracy of power data depends on the data plugged in. I outlined in detail in my presentation at ARM DevCon how this works. Developers use budget data, estimates (like the ones created from high level synthesis J) or data from previous projects. And the data can be refined once more detailed information is available during the design flow.

So in summary, I think Ran and I agree that early power estimation is important. Adding high-level synthesis makes a good flow. Our means are different but no solution is universal.

And finally, Ran, my daughter says “Hi”. She is not afraid of snakes, especially when they are as friendly, fast and early available as virtual platforms. 




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