A View from the Top: A Virtual Prototyping Blog


On Chameleons, Low Power and the Marketing Power of Copy Editing

Eric Carle's ChameleonI had an epiphany while reading Eric Carle stories to my three year old daughter. And boy is she is smart! She figured out for me at her young age already the power of marketing in positioning high technology. Bottom line: What you read is not always what you will get once you buy it. But we already knew that, didn’t we?

Eric Carle’s books are great. There is his story of the Mixed-Up Chameleon and I read it to my three year old daughter the other day at bed time. It is about this chameleon who wants to be somebody else. So it asks for a bird’s wings, flamingo’s long legs, an elephant’s nose and a frog’s tongue etc. It’s a quite well done portrayal of wanting to be something or someone you are not. I have to admit that I was slightly distracted because my presentation for the ARM Developer’s Conference was (over)-due and I had planned to finish it that night. The topic I was to talk about was low power analysis at the system-level.

During the day I had reviewed competitive announcements and was still thinking about an admirably marvelous, textually beautiful written press releaseclaiming to now address “designers’ next critical need – faster power exploration and estimation – earlier in the product design lifecycle”. The products in question now would enable “SoC designers, architects and validation engineers to quickly estimate the power consumption of their system during the design phase, analyzing the effects of running various real software stacks and other real-world stimuli.” And there is more, the two products in question combined would “provide automated processes and capabilities early in the design process, taking in consideration the technology libraries, the embedded software and the real stimuli to ensure system power budget constraints are being met with the real environment at first silicon with first working software phase”. All of it provides the “unique ability to analyze and verify power tradeoffs at the point where hardware and software design converge – the system level”.

Well, all that is quite a mouthful. Can I counter that? I am a firm believer that going to the system-level is crucial, but why them? Sniff. That’s when my daughter’s question hit me:

“Papa, will the Chameleon’s new tongue for fly-catching work while it is flying with the bird’s wings”? It turns out, she was way ahead of me!

Power consumption component of a multimedia phoneLet me roll back a bit … My talk at the ARM Developers Conference was titled “Software Driven Low Power Optimization for ARM Based Mobile Architectures”. It stems from discussions I had with customers and users for years now.

When users do system-level low power analysis, inevitably they will start with spreadsheets capturing high level information. Like in the design illustrated in this figure, which I analyzed in more detail using all the available datasheets a while ago, all the different components in the system have power consumptions associated with it. The same is true of course for the individual blocks in the various chips involved. The challenge with a spreadsheet is that it is static and does not execute any software stacks to actually trigger the many different power states such a design can be in.

Later in the design flow users will arrive at the RTL stage. Everything is now coded in the RTL mix of function and micro-architecture. Users can run analysis with logic synthesis and tools like Power Compiler. In an emulator or hardware prototype, RTL can be executed and software stacks can be run with it. Now the accuracy is much better and real software can run on the RTL given sufficient hardware support, but the ability to make trade-offs is very, very limited. The amount of effort it took to first write the RTL, to then verify it and even bring it up on hardware, altogether is so prohibitively expensive that in most cases fundamental architecture changes are hopeless at this point.

Bottom line, the issue articulated to me by users is that (1) spreadsheets unfortunately do not execute software and (2) when things are integrated at the RTL level all the important partitioning decisions are already made.

My talk at the ARM Developers Conference gave an overview how we at Synopsys address this issue using virtual platforms. In brief, we do allow users to enable virtual platform components for low power by exposing different power states. Different power states of CPU load as well as states for peripherals and even the actual energy consumption cost per memory write and read can be easily added in. During the execution of software the system switches through its different power states in all components and a central power accumulator combines this information into actual power and energy values. This level of power analysis and estimation positions itself well between the abstract, static spreadsheet and the RTL simulation at which actual power consumption can be measured. As outlined and in detail discussed in a whitepaper I wrote not too long ago, these virtual platforms are based on TLM-2.0 model re-use and developed from the textual specifications. As such they are available long before RTL or silicon are available, often as early as 9 to 12 month depending on the complexity of the design to be modeled.

At this point my three year old daughter – her eyes already almost closed – dozes off with the words “I think he cannot use his tongue to catch flies while he is flying with his wings”. While trying not to doze off myself … need to get that presentation done – I am happy and relieved that even beautiful writing cannot hide the three basic facts coming from all this.

  • Static spreadsheets allow architecture trade-offs but only without software – which they simply don’t execute.
  • RTL co-simulation with software is too late in the flow to allow meaningful architecture trade-offs. If you discover at this stage that the architecture has to be re-done to meet power envelopes, your career as project manager is at risk of coming to a potentially very abrupt and fast end.
  • Power enabled virtual platforms are the way to go for early power analysis taking into account software. They are where hardware and software first meet. They can be done long enough before RTL to allow meaningful feedback into the architecture.
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