Posted by frank schirrmeister on July 7, 2008
Happy post 4th of July. Even though I am only a German observer, I did enjoy the fireworks! The last two weeks have been interesting to say the least. After the Freescale Technology Forum I immediately left for a trip San Francisco – Tokyo – Bali – Tokyo – Frankfurt – Hamburg – Berlin – Frankfurt – Tokyo – San Francisco, all in 10 days. Our mid-year sales update took place in Bali (I know, your sympathy is gone by now) and the trip to Germany was to attend my Dad’s 70th birthday. Both events gave me enough opportunity to try to explain in Laymen’s Terms what my job and system-level design is all about. While lost between two buildings in the hotel resort in Bali I had the idea to explain it in hotel terms. Here it goes:
Assume you are the hotel business on Bali (As a disclaimer – I am not – I just enjoyed staying here for our sales training and have no connection to Hyatt). Life is good and you are planning a new hotel location. The terrain has been defined and the deal looks good. Here are two drawings of the hotel I stayed in while on Bali. One is high level structural and one is more detailed. With which one would you start your planning?
Right, in the higher level of abstraction of the structural diagram it is much easier to define the intent of the hotel plan without getting caught up in the details. At this level you have defined that you need four living complexes with a specific number of rooms. You need a spa, a pool area, a conference center, shops and restaurants and finally administrative buildings, parking and sports facilities. You define the different main hotel units and their interfaces. This is exactly what the system-level designer does for chip design, he defines the big blocks, some of which the implementation team buys as pre-defined units (Intellectual Property – IP) and some of which the team then implements from scratch. In our virtual hotel planning exercise we have constraints like “that many people will have to go to breakfast between 7am and 10am, we better have appropriate pathways to help them transfer”. Chip designers face similar issues, they have to understand the dimensions of data traffic going on between different blocks and make sure the appropriate connections or bus-systems are available.
So it is all about the different units in the system and the interfaces between them!
What is interesting now is when a different abstraction levels are required, i.e. when a developer naturally switches to the next level of abstraction. What is defined in our Bali hotel exercise in about 12 blocks and some constraints, takes at the next level down at least 120 lines to draw. So there is roughly a factor of about 10 somewhere in here to allow entering the information in an abstracted way.
Synopsys fellow Mike Keating of the Advanced Technology Group pointed to that same factor 10 in a presentation given at the most recent Design Automation Conference 2008 titled “Simplicity and Complexity – The challenges of human-centric design in the era of billion gate SoC’s”. The EDA industry has successfully built tools to automate the transfer between abstraction levels sufficiently. This is also in sync with a basic paper from 1956 “The Magical Number Seven, Plus or Minus Two: Some Limits on Our Capacity for Processing Information“, in which George A. Miller successfully shows data that the human brains is simply not able to process more that 5 to 9 things at once, so abstracting upwards when one reaches ten makes sense.
Take away from all this is twofold. First, it is crucial to find the right level of design entry and that is what system-level design is all about. With the next abstraction level, the transaction-level, the EDA industry is in the midst of a transformation, but we are probably still in the beginning stages for mainstream automated design from the transaction level. Second, given that this is the 7th paragraph of this post I better stop so that you have a chance to remember them. And yes, the Grand Hyatt Bali as shown here is worth the trip and I enjoyed it very much. I just made the mistake to be there only two days for work … next time I’ll stay longer.
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.