Posted by frank schirrmeister on June 12, 2008
On Wednesday Mentor hosted its 6th Annual ESL Symposium here at DAC. The panel gave a great overview of the ESL space. ESL Synthesis and Virtual Platforms for pre-silicon software development seemed to come out as the two areas of ESL with the most adoption so far.
Wally Rhines opened the panel and reminded the audience that this market has grown from $70M in 2000 to over $200M in 2007 according to EDAC data, i.e. data which the EDA vendors actually report. So, while we were not looking the market has actually grown to over $200M already.
According to survey data cited, 70% use high level synthesis and 23% use TLM based verification. The main drivers are (a) Design Complexity with 16% of designs using more than 3 processors, 11% having more than 21 clock domains and 22% more than 10MGates of logic and data path, (b) Verification with 60% of re-spins have functional causes, (c) low power and high performance and finally (d) time to market.
Wally added that originally the ESL investments were in modeling, system analysis for performance and virtual prototyping. Now ESL models can also be re-used in TLM verification and ESL synthesis. Low power was quoted by Wally as “probably the biggest driver”.
First panelist to present was Viraphol Chaiyakul, Senior Director of Engineering in the QCT SoC Platform group. He gave a snapshot of the ESL adoption at Qualcomm. They differentiate verification, analysis and design. In verification Qualcomm already uses TLM-based hardware functional verification, software driven verification and early software validation. Model sharing and reuse by way of standards is next – they will adopt SystemC TLM-2.0.
In analysis Qualcomm does a lot of non-functional, traffic based trade off analysis and estimation. Going forward they need tools to allow quantification and definition of model accuracy and fidelity. They also propose a meet-in-the middle approach for modeling combining characterization and estimation.
The design area today uses block synthesis and simulation platforms for hardware software co-development. The key challenges are to make the ESL models golden, to verify the ESL models and to measure the quality of results. Going forward they look for synthesizable and verifiable TLM-2.0 flows.
Next up on the panel they had Prakash Rashinkar, Director of Engineering at Rambus. He talked about performance analysis for memory technologies. He introduced memory as the bottleneck with the skyrocketing data rates for memory accesses combined with advanced access and protocol techniques. ESL performance models are used at Rambus to design and validate complex access protocols. Prakash also pointed to SystemC TLM-2.0 as an important step. In summary for Rambus ESL is a key step to unleash XDR performance, it supports top down design, which in turn is accelerating time to market and enables re-sue of test environment for verification. ESL is a must have technology for them.
Kaz Yoshinaga, Researcher at STARC, was up next and he pointed to interoperability issues of transactions between vendors and the resulting importance of standards. Based on OSCI and additional application standards STARC introduced a transaction-level modeling guide separating communication from computation including a refinement path from un-timed to timed models. They confirmed that the models can be imported into major system-level tools. Transaction-level design is a common ground for successful methodologies. The first edition of the STARC guide is available and will be upgraded to support TLM-2.0 in early 2009.
Nitin Chawla, Senior Member of Technical Staff at ST followed as the next panelist. He focused in ESL synthesis. In their SoCs the application engines like video codecs and wireless modems create most of the differentiation. They start with C/C++ models and use high level synthesis to automatically create the RTL which they validate using simulation technologies. Next generation sequential equivalence checking will increase confidence for them. Design productivity improvements can be 5x compared to RTL. Combined with high-level model reuse they can reach about 10x productivity improvements. He called for better memory analysis and trade-offs to be able to explore a bigger design space. ESL synthesis is reality for ST, have done a large number of production designs. Key benefits are productivity flexibility and improved QoR.
Final speaker was Bernard Candaele, department head of SoC, IC & EDA at Thales. He introduced their project focus on high complexity system developments like the Galileo satellite navigation systems. They have several candidate platforms and use early software execution on virtualized platforms. In addition they are using ESL synthesis in some of their designs. The next challenge will be the maturation of tools and links to verification. Bernard mentioned a debate between HDL designers and ESL engineers as the methodology shift has impact on the design population.
Bottom line ESL synthesis and virtual platforms, combined with some performance analysis were the main drivers outlined among the panelists. The following discussion was largely moderated by Wally. The biggest factors to drive towards ESL adoption cited were management of design complexity, productivity and time to market pressures. For Prakash at Rambus the ESL performance models enable education of customers and even sales support. SystemC was quoted as the biggest advancement in EDA to make ESL possible. All panelists confirmed that SystemC TLM-2.0 is an essential step and ready for adoption right now.
In summary this panel gave a good update on the different areas of ESL usage – it is here today! ST pointed out that in some of their divisions 90% of the new IP blocks are now designed with high-level synthesis! SystemC TLM-2.0 came out as the unquestioned next important step at the transaction level – both for hardware verification and virtual platforms enabling software development and verification. Key challenge going forward will be verification of ESL models themselves to make them golden.
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.