Posted by frank schirrmeister on June 9, 2008
Well, we are here, finally! After Synopsys contributed key technologies in early 2007 the age of proprietary virtual platforms seems to come to an end with the announcement that the TLM-2.0 API for transaction based interoperability has been finalized. We at Synopsys immediately announced that we are fully endorsing the standard and that we will support it in our DesignWare System-Level Library and Innovator product lines.
Why is this important? Well, over the last decade the virtual platform industry with the three V’s Virtio, VaST, Virtutech combined with ARM-AXYS and CoWare have basically saturated the early adopters in this market. What was hindering the market to further proliferate is now no longer an obstacle – the interoperability of models. As indicated in this figure the introduction of TLM-2.0 is really like the standardization of Verilog and VHDL which eventually led to the demise of proprietary HDLs. With the introduction of TLM-2.0 the proprietary APIs for fast virtual platform development will eventually be replaced with SystemC TLM-2.0.
The Fujitsu quote in the Synopsys press release says it all:
“We recognize the need for system-level solutions that improve the efficiency of pre-silicon software development as well as complete system verification, and interoperable models are key. The TLM-2.0 compliant SystemC models delivered in Synopsys’ DesignWare System-Level Library are a valuable piece of an ESL design methodology enabling the rapid development of virtual platforms.”
Director, ESL & Verification Department, SoC Design Engineering Division
Fujitsu Microelectronics Limited
So, technically, what are the key deliveries of TLM-2.0, for which the OSCI announcement has been endorsed in its quote sheet by almost 30 companies?
TLM-2.0 defines the interoperability standard that allows model reuse for software development and performance analysis as well as architecture analysis. The actual features supported include generic transaction payload for memory mapped busses with payload extension mechanisms allowing users to instrument their virtual platforms with timing in loosely timed (LT) and approximately timed (AT) modes. The adoption of TLM-2.0 minimizes the need for bridges or adaptors to connect models together and it supports multiple, compatible abstraction levels. As a result users get high simulation speed, debug and analysis and interoperability with the earlier versions of TLM-1.0.
Documentation, training and examples are available for download from http://www.systemc.org/home.
We will have a user panel discussion with the theme “Real World Advantages of the OSCI TLM-2.0 Standard for Model Interoperability and IP Reuse” today at 12:00 noon in Ballroom E of the Anaheim Convention Center. I will let you know what these users have to say. For the time being I am leaving you with a positive outlook on the virtual platform market by quoting Gray Smith from our Synopsys press release:
“In our 2007 ESL Market Trend Report, we predicted more rapid growth for virtual platforms once the standards issues get resolved. Standardization of TLM-2.0 removes an important hurdle for virtual prototyping to enter mainstream adoption and to more closely link embedded software and hardware development.”
President of Gary Smith EDA
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.