Posted by frank schirrmeister on June 9, 2008
I am at the Design Automation Conference here in Anaheim this week. While my three-year old daughter has her first Disneyland experience (go princesses!) I am attending several sessions and panels, but will mostly interact with customers.
The Sunday here at DAC kicked off with the EDAC Executive Reception, which was distinctively different this year. After the typical networking they had brought on a panel with the game show theme “It’s Time to Play Differentiation” moderated by Ron Wilson. Wally Rhines played a fictitious OEM trying to differentiate a design and let the vendors push their buzzers to explain how they would differentiate. Wally came up with requirements for the “MyPhone”, a smart phone consuming very low power, having an HD display, supporting any broadband source in any country and also being an open platform, i.e. independent vendors can add applications.
Representatives from Virage, TSMC, Synopsys, Magma, ARM and Analog Bits were commenting in an entertaining way on their differentiation prompted by riddles coming from Wally. Well, what we already knew in the Synopsys SLS team – that it’s all about the models – came true here as well. Given that all this happened in Southern California, two quite eye-catching models (female and male to keep the balance) were brought in to present various envelopes, applause signs etc. I can’t really post pictures without getting in trouble with our Marcom police, but use your imagination.
Bottom line though several ESL related issues were emphasized really well – design for low power, design flexibility with multi-standard support and support of an open platform for programming! Oh, and the Industry’s Gadfly John Cooley got voted off the EDA industry in the process. He seemed to have re-appeared though later in the evening.
The evening continued with the General Chair’s Reception. Opening speaker was NVidia’s Chris Malachowsky with a pretty cool talk about the power of heterogeneous computing, their Tesla GPU architecture and the CUDA programming model to allow efficient programming of multicore architectures.
From a system-level perspective the CUDA programming model is an interesting one to follow as we seem to arrive at several new programming models for the different application segments. CUDA is especially effective for graphics applications, but Chris also reported impressive 17x to 149x improvements in performance for other applications like physical computing and signal processing.
Next on was Mary Ann Olssn from Gary Smith EDA asking the question “whether this is the year of analog?”. All industry indicators seem to imply that it is …
Bryan Lewis from Gartner talked about the transformation of the ASIC domain, nicely summarizing major industry trends like acquisitions (LSI: Agere, Marvell: Avago), TI’s exit from leading edge process development and Nokia’s outsourcing of ASIC design to ST. The key outcome seems to be that nobody can do it alone in the semiconductor industry anymore and that the actual system-level knowledge is shifting around with ASSP providers again doing more ASIC like designs and system companies doing less chip design.
As a result Bryan sees a fragmentation of the ASIC market between leading edge designs producing big dollars and mainstream designs using older processes (especially in Asia Pacific). He foresees further supplier consolidation at 32nm ASIC designs. In addition design reuse will increase with more ASICs being derived from ASSPs and finally vertical application focus will be crucial with software supporting it on platform based products with lots of unique IP.
Last on stage was Gary Smith from Gary Smith EDA. His presentation was titled “FUD, Reality and Vision”. First Gary addressed some of the FUD around. He attributed the alleged semiconductor recession to memory pricing problems and countered the claims that there may be only a hand-full of Fabs in the near future with the prediction there will be a handful Mega-Fabs and Mini-Fabs making a comeback. Instead of the often predicted further consolidation of the semiconductor market, Gary took the position that there will actually be an expansion, with many of the older semiconductor vendors disappearing and being replaced primarily by Asian semiconductor vendors.
Finally Gary countered the notion of the EDA industry maturing with the information that they added 62 new EDA vendors to their analysis. Gary sees only the RTL portions maturing but not ESL, which grew 50% in 2006 and is projected to have a 47.4% five year CAGR. Exciting times for ESL!
On embedded software Gary showed an interesting analysis based on the software cost chart coming from the 2007 ITRS data . He took the graph on the right, Figure DESN1, “Impact of Design Technology on SoC Consumer Portable Implementation Cost” (from page 2 of the report on design) and re-drew it assuming the industry does not deal with parallel processing , assuming that there will be no concurrent SW compiler partitioning software across multiple cores and assuming that the industry does not deal with heterogeneous parallel processing. The resulting, modified graph had a peak in 2015 with an overall development total being at around $500M (compared to less than $100M with productivity improvements) and software development consuming the lion share of it. Well, let’s hope we all will figure it out and can avoid such an disaster …
Gary closed with a list of top ten issues for 2008. Among them were tools for multicore programming (2), a new embedded software language (3), FPGAs becoming a true system development platfom (5), intelligent test bench (6), the battle for the virtual platform market (7) and the question on how to reach 80% to 90% die re-use (10). This means that more than half of the top ten issues are predicted to be system-level issues!
In summary the evening left one with the impression that embedded software and electronic system level issues are key drivers over the next years to come. This promises to be an interesting DAC for ESL again!
Patrick Sheridan is responsible for Synopsys' system-level solution for virtual prototyping. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). Mr. Sheridan has 30 years of experience in the marketing and business development of high technology hardware and software products for Silicon Valley companies.
Malte Doerper is responsible for driving the software oriented virtual prototyping business at Synopsys. Today he is based in Mountain View, California. Malte also spent over 7 years in Tokyo, Japan, where he led the customer facing program management practice for the Synopsys system-level products. Malte has over 12 years’ experiences in all aspects of system-level design ranging from research, engineering, product management and business development. Malte joined Synopsys through the CoWare acquisition, before CoWare he worked as researcher at the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany.
Tom De Schutter
Tom De Schutter is responsible for driving the physical prototyping business at Synopsys. He joined Synopsys through the acquisition of CoWare where he was the product marketing manager for transaction-level models. Tom has over 10 years of experience in system-level design through different marketing and engineering roles. Before joining the marketing team he led the transaction-level modeling team at CoWare.