A View from the Top: A Virtual Prototyping Blog

 

May you live in interesting times …

Well, even though Robert F. Kennedy referenced this phrase as a Chinese proverb in 1966, the origins do not seem to be Chinese though. For us at the front end of chip and system design however, at the system-level times hardly could be more interesting.

My favorite graph to illustrate the history and the trends where designers are going with abstraction levels is shown below. I drew this first for Alberto Sangiovanni Vincentelli back in the late 90’s and it has seen many incarnations since then.

The history and future of abstraction levels, abridged.

Over the past decades mainstream design entry has moved up from layout to transistors to gates and eventually to RTL. The driving factor for each transition was the complexity of the designs under development, which made it unfeasible to actually stay at the respective lower level of abstraction. Since the mainstream adoption of Verilog and VHDL as languages for design at the register-transfer level (RTL), the next level of abstraction has been in development, so to speak. Gary Smith – at the time at Dataquest – coined the term “Electronic System-Level Design”, ESL, for the technologies beyond RTL. From there on different definitions of ESL were in the making. I’ll try one myself later on but for the time being … we really do live in interesting times as we are marching through the platform based design towards Multiprocessor Systems on Chip (MPSoC), where in a sea of processors software is distributed across them.

One key technology to enable design at the next level of abstraction is leaving the age of proprietary solutions and by way of standardization is now ready for mainstream adoption. Virtual platforms – fully functional models of the system under development – have been using proprietary languages for the last decade. They have several use models, the main one being pre-silicon software development, which can be done on a virtual platform often 6 to 9 month prior to silicon availability. While in the land of proprietary languages they found some respectable adoption from customers who had enough pressure to adopt proprietary solutions. However, they were lacking interoperability and that was certainly an inhibitor for mainstream adoption.

In early 2007 Synopsys decided to contribute technology coming from the Virtio acquisition to OSCI. After two years of work OSCI is now getting ready to roll TLM-2.0 out! With that finally the appropriate technology is in place to allow interoperability of models between SystemC compliant simulators, opening SystemC to fast multicore virtual platforms for early software development and verification. This marks a major milestone, certainly just as significant as the adoption of Verilog and VHDL was in the 90’s.

Times will become even more interesting going forward and this Blog will deal not only with the shift towards adoption of virtual platforms but with ESL technologies in general.

I am looking forward to hearing from you!

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