To USB or Not to USB


The World’s First Demonstration of SuperSpeed InterChip (SSIC)

Synopsys worked with the USB-IF SSIC Working Group to develop a SSIC Proof of Concept demonstration. 

The USB-IF has been working on SSIC for some time.


This Proof of Concept in FPGA is to test the SSIC specification version 0.90 to see if it actually works in hardware.

It worked (mostly).


We learned, as expected, the SSIC Spec needs changes.

We learned what works and fixes need to be made to the specification.

We used our own HAPS FPGA platforms and standard PCs.  The HAPS51-2s are connected to the PCs with PCIe.  The FPGA boards are shown below.


On top (left side of table) we have a modified USB 3.0 Host for SSIC.

On bottom (right side of table) we have a modified USB 3.0 Device for SSIC.

There is no USB 3.0 PHY in this set up.  Read to end for more on the PHY used.


Take note:  FPGA-Based Prototyping is a good idea as part of specification development too.

As with our standard USB 3.0 Host and Device, we could close timing in the FPGAs at 125MHz even when the FPGA design is over 80% utilized.


We’ve edited 2 versions the SSIC Proof of Concept video for your viewing pleasure. 

A short version and a long version.


The short version focuses on the hardware setup and the demonstration.  It’s posted below.

SSIC Proof of Concept – Short Version


This is Shailesh and I just before we started the demo.

What is the point?

The SSIC USB-IF WG has both proven the SSIC concept works, and improved it using FPGA-based prototyping.  The USB 3.0 can be used with the SSIC modifications to use USB 3.0 on PCB for chip-to-chip communication with less power than USB 3.0 outside the box.  It preserves software so you continue to use existing USB 3.0 drivers and stacks.


What is SSIC?

See the previous entry here for a brief description.

It will be used to connect Applications Processor chips to other USB 3.0 peripherals inside the box, on PCB.  It is a chip-to-chip protocol. 

For example, it could be used to connect a Mobile Apps Processer to a WiFi baseband chip.  The Apps processor could use the same, unmodified USB drivers it uses for an external, USB plug in WiFi modem.   It uses USB 3.0 to communicate, but it can less power because it drives signals over a few centimeters of PCB, not 3 meters of USB 3.0 Cable.  SSIC uses a different M-PHY for SSIC.   It uses less power.  We don’t use an M-PHY in the SSIC Proof of Concept.


Caveat and Disclaimer

This is not a product and this is not a product announcement.  This is a working demonstration of the technology.


Read to the End

The long version is 7 minutes and has a lot of detail and is only for the most brave USB viewers.   It has a more detail detail on how the two boards are connected.  So I lied.  There is no detail how the two platforms are connected when the USB 3.0 PHY is not used. You have to wait until Thursday and watch that video.

See you Thursday.



This Blog Address moved to:


I wanted to post the short video first and post the long video later, but someone pointed out to me that no one is going to ever watch these videos twice.

So I separated them anyways because you were going to come back on Thursday anyway.

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