To USB or Not to USB

 

Renesas doubles USB 3.0 Host production, USB & DDR Jobs at Synopsys

After shipping 30 Million USB 3.0 Host chips, Renesas says:

“…to further address increasing orders from customers, it plans to double production of USB 3.0 host controllers to a monthly production of six million units starting this June.”                                                             ———– Renesas Press Release May 23, 2011

So that means that Renesas will ship ~57 million units by the end of the year.

The entire PC market (all PCs) is about 300 Million units, or about 20% of the PC market for Renesas.

According to BrightSideofNews.com, the NEC/Renesas chip has over 90% market share today.  If the market grows, we could see a lot more that 57 million hosts ship.

Serious competitors will compete hard for chips so maybe USB 3.0 Host pricing will drop.

The announcement of higher production from a Japanese company, means that competition is already happening.  Renesas is responding to increased demand.  Maybe locking up customers as quickly as possible.

I’m guessing that Renesas’ competitors are also locking up customers.  The point is more mainstream laptops and PCs will get USB 3.0 as a standard, in advance of USB 3.0 in chipsets.

Okay, now the fun part.  3 jobs at Synopsys.

 

2 USB jobs & 1 DDR job at Synopsys

Job 1 – USB, Senior Manager, Customer Applications Engineer

Requisition Number – 1850BR
Location: USA – California – Mountain View/Sunnyvale

Description

    As a lead Corporate Applications Engineer (CAE) in the Solutions Group, you will manage a team of dynamic and highly skilled CAEs that provide technical support to  customers of DesignWare USB2.0 and USB3.0 Controllers. You will work closely with customers using the DesignWare USB IP and support them through various design stages from integration to Silicon debug of their chips and ultimately be responsible for customers’ success using Synopsys USB IP. Responsible for generating technical collateral, application notes, etc and representing DesignWare USB IP at key technical conferences and events. You will also work closely with R&D & Marketing teams to participate effectively in product enhancement, new release processes, development of alpha test plans, representation of customer issues and other core team activities.  Will lead and manage a global team of highly dynamic CAEs to achieve goals and/or resolve technical problems.

Requirements

BS, MS with 10+ years in the field of ASIC design with at least 4 years of Management experience. Candidate must be highly independent with a “can-do” attitude and a proven track record of deep expertise with USB Controllers and ecosystems. A strong understanding and extensive experience in overall ASIC design process is required. Domain knowledge of USB protocols is a must. Technical background and previous experience with digital design including USB Silicon/Software Debug experience is highly desirable. Excellent communication skills a must. Occasional travel may be required.

 

Job 2, Senior Customer Applications Engineer

Requisition Number – 1851BR
Hiring Location(s) – JAPAN – Tokyo

Job Description

As a member of the Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customers using Synopsys DesignWare digital USB IP. You will interface directly with customers to solve design issues or questions related to USB IP products, product installation and training, and work with Sales, Marketing and R&D to drive existing and new product evolution. You will have the capability to design and implement solutions to complex applications problems independently with little guidance. You will author application-notes and/or white-papers that promote the IP’s ease of use, or address specific challenges in the IP’s usage . You may be called upon to author technical papers and present them in peer-reviewed technical publications or conferences.  You will have regular contact with external customers and internal contacts across cross-functional teams in various geographies.

Requirement:

Qualified applicant will have a BSEE 9+ years or MSEE, + 7 years relevant experience in ASIC/FPGA design of communications or consumer applications. An understanding of system design and logic design using an HDL language, synthesis, simulation and verification CAD tools and tool flow is important. The ability to conduct technical presentations and product demonstrations to customers is needed. Strong written and verbal communication skills in Japanese and English languages, ability to work independently and problem solving skills are an absolute requirement. Must have experience with USB protocols – USB 1.x, 2.0, preferably USB 3.0 also. Occasional travel may be required.

Job 3, Senior Customer Applications Engineer

Requisition Number – 1849BR
Hiring Location – USA – California – Mountain View/Sunnyvale

Description

    As a Corporate Applications Engineer (CAE) Manager in the Solutions Group, you will manage a team of dynamic and highly skilled CAEs that provide technical support to  customers of DesignWare DDRn Digital and Mixed Signal IP (DW DDRn IP). You will work closely with customers using the DesignWare DDRn IP and support them through various design stages from integration to Silicon debug of their chips and ultimately be responsible for customers’ success using Synopsys DDRn IP. Responsible for generating technical collateral, application notes, etc and representing DW DDRn IP at key technical conferences. You will also work closely with R&D & Marketing teams to participate effectively in product enhancement, new release processes, development of alpha test plans, representation of customer issues and other core team activities.  Will manage a global team of CAEs to achieve goals and/or resolve technical problems.

Requirements

BS, MS with 10+ years in the field of ASIC design with at least 3 years of Management experience. Candidate must be highly independent with a “can-do” attitude and a proven track record of deep expertise with DDRn Controller and PHYs. A strong understanding and extensive experience in overall ASIC design process is required. Domain knowledge of DDRn protocols is a must. Technical background and previous experience with mixed-signal/analog design including Silicon Debug experience is highly desirable. Excellent communication skills a must. Occasional travel may be required.

Go to the Synopsys website if you would like to apply on line.  If you’d like to talk to me, contact me through LinkedIn (only because I
don’t want to post my e-mail address here).

Next Time: SSIC and MIPI – or SuperSpeed InterChip and why you should care. And the answer to the question. (Really, I will talk about it)

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