There is chatter in the standards arena that unless the 3 biggest EDA vendors can agree at the outset, a standard cannot be successful. What an innovative way to block standardization! I cannot recall, in any organization, that there was agreement at the beginning of a standards effort. Some disagreements were more heated than others, […]
Posted in 2. Skirmishes, Battles and All-Out Wars, 3. Duh. | Comments Off on Why Must We Be Friends?
When it comes to VHDL, the line from Monty Python and the Holy Grail always pops into my mind, and I want to cry out (in a strong British accent), “But it ain’t dead yet!” VHDL is indeed alive and kicking. Some even argue that VHDL has always been the ultimate system-level design language. While VHDL’s market […]
Posted in 1. Life in the Standards Lane | Comments Off on VHDL users can capitalize on SystemVerilog now
In a recent comment posted on JL Gray’s “Cool Verification”, Dennis Brophy (my counterpart at Mentor Graphics) asked about terms and conditions for access to VMM. I’d like to address his concerns for today and tomorrow. The Verification Methodology Manual (VMM) is a published book, co-authored by ARM and Synopsys that anyone can purchase today. It includes the verification […]
Posted in 2. Skirmishes, Battles and All-Out Wars | Comments Off on Accessing VMM – today and tomorrow
More and more, users (customers) are demanding one standard verification library. As a result of this growing interest, Accellera will start investigating the feasibility of creating a single, SystemVerilog verification library. My company, Synopsys, is committed to support our customers’ interoperability requirements. We are ready to fully support an Accellera initiative, contributing our technology and expertise towards a single […]
Posted in 2. Skirmishes, Battles and All-Out Wars | 10 Comments »
Experienced standards people know there are certain aspects of standardization that just plain work. When they’re not followed, trouble often ensues. Progress can be delayed, valuable resources can be wasted, or a standard might be produced that no one ever uses. Based on real activities I’ve been involved in that were either quite successful or dismal failures, I […]
Posted in 6. The 10 Commandments | 4 Comments »
If you aren’t already planning to attend, I encourage everyone interested in modern IC design and verification to attend DVCon 2008. DVCon, the unique Design and Verification Conference sponsored by Accellera, continues to provide the latest on methodologies, techniques, and (of course) standards that improve engineering productivity and IC quality. Registrations are up, the hotel […]
Posted in 4. Be There or Be Square | Comments Off on DVCon 2008 – the best yet!
