Posted by Tom Borgstrom on November 2, 2009
This is going to be a pretty boring post, without much drama. But, I think that’s OK (once in a while). Let me explain.
In the world of national and international politics, sensational news of conflict often gets more media attention than stories of cooperation, collaboration and progress. Much the same happens in the world of electronic design automation, albeit at a much smaller scale. Editors and bloggers alike are drawn to controversy, like moths to a light, in an effort to get more readers or pump up circulation. Verilog vs VHDL! Vera vs. Specman! SystemVerilog vs. SystemC! VMM vs OVM! Some readers are also drawn to this for the vicarious thrill of seeing their favorite company or technology face off against an opponent. It’s hard not to get caught up in it! Sometimes these debates actually help drive progress and consensus, but very often they are based on a false argument and end up annoying chip developers who just want to get their design out.
Stories of cooperation and interoperability tend to get less airtime amongst the media, perhaps because it is expected that companies will just make things work. In the developed world, nobody writes stories about how the lights turn on or the phone works or the water runs. However, I’d say that the EDA industry is not quite as developed as the public infrastructure in advanced countries. Complex chip development technologies created by independent, competing companies don’t “just work” together without consistent focused effort and significant involvement from end users.
This Thursday (November 5) in Santa Clara, Synopsys will be celebrating the progress made over the past year in EDA interoperability and standards at its 22nd EDA Interoperability Forum with the theme “Peace, Love and Interoperability”. This all-day event, held at the Sun Conference Center at Agnes Historic Park, is open for both EDA tool developers and IP/chip developers.
The agenda includes quite a bit for verification-minded folks: learn the latest developments around SystemC TLM 2.0 for interoperable system-level models, the latest VMM methodology updates for interoperable verification environments, and the HapsTrak interface for open connectivity to FPGA-based rapid prototypes. As an added bonus, the first 100 attendees will receive free copies of the VMM for Low Power book, and Doulos’ VMM Golden Reference Guide.
Registration is free, and breakfast and lunch is provided. I hope to see you there!
Who knows what the future will bring! After implementing neural networks in analog CMOS for my MSEE at Ohio State, I moved to Japan to do digital ASIC design using the new VHDL language and fancy logic synthesis technology from a startup called Synopsys. This introduced me to the wonderful world of EDA, where I was able to explore lots of other cool new technologies from test automation at CrossCheck to FPGA synthesis at Exemplar to code coverage at TransEDA to testbench automation and methodology at Synopsys. Twenty years flew by in the blink of an eye!
I am starting a new exploration around the bigger picture of what it takes to verify and validate increasingly complex designs on increasingly compressed schedules and budgets. This broad topic ranges from technology to economics, from embedded software development and architecture analysis to RTL and circuit design; from personal productivity to distributed team efficiency; from novel ideas to fundamental paradigm shifts; from historical perspectives to predictions of future requirements. Please join me and share your thoughts on verification!
- Tom Borgstrom