Posted by Tom Borgstrom on October 12, 2009
After a long break from On Verification, I’m back at it again now with today’s rollout of Synopsys’ latest synthesis tool – Synphony HLS. “Synthesis? I thought this blog was On Verification” you may ask. Let me explain.
As I’ve said before, software development and verification are the two biggest and fastest growing parts of the total cost of chip design. With chip development cost approaching $100m on advanced process nodes, any technology that improves productivity of software and verification teams can have a huge payback. High level synthesis (HLS) is one such technology.
In general, HLS raises the level of abstraction for design, enabling verification to also be done at a higher level and reducing downstream verification effort. With “correct-by-construction” generation of RTL and other views, more verification effort can be applied at higher levels without having to be repeated for RTL. This means designers can quickly explore many architectures (i.e. build the right design), write fewer lines of synthesizable code (i.e. code fewer bugs) and rapidly simulate complex functionality (i.e. complete verification sooner). So, HLS can be an important technology for chip developers looking to manage growing verification costs.
So, how does Synphony HLS fit into the world of high level synthesis? First of all, Synphony HLS is targeted at communications and multimedia chips with high algorithmic content – a large and growing market. Designers of these chips typically do algorithm development in the M-language using untimed, floating-point code. To reach silicon these engineers have to manually re-code their algorithms into fixed-point architectures and then re-verify – a time-consuming and error-prone process. Synphony HLS changes all of that by automatically synthesizing floating-point M-code into fixed-point RTL that is optimized for power, performance, area, etc. based on user constraints. We all know that “one size” of RTL doesn’t fit all, so Synphony HLS generates RTL targeted at the intended use – ASIC synthesis, FPGA synthesis or FPGA-based rapid prototype. Synphony HLS also generates a C-level representation of the fixed-point algorithm that can be used in virtual platforms for early software development. There’s nothing else in the market today that does all of this.
So, while today’s announcement is about high level synthesis, it is really exciting news for verification as well!
Who knows what the future will bring! After implementing neural networks in analog CMOS for my MSEE at Ohio State, I moved to Japan to do digital ASIC design using the new VHDL language and fancy logic synthesis technology from a startup called Synopsys. This introduced me to the wonderful world of EDA, where I was able to explore lots of other cool new technologies from test automation at CrossCheck to FPGA synthesis at Exemplar to code coverage at TransEDA to testbench automation and methodology at Synopsys. Twenty years flew by in the blink of an eye!
I am starting a new exploration around the bigger picture of what it takes to verify and validate increasingly complex designs on increasingly compressed schedules and budgets. This broad topic ranges from technology to economics, from embedded software development and architecture analysis to RTL and circuit design; from personal productivity to distributed team efficiency; from novel ideas to fundamental paradigm shifts; from historical perspectives to predictions of future requirements. Please join me and share your thoughts on verification!
- Tom Borgstrom