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Verification Methodologies: Standards will come; in the mean time get that chip verified!
Posted by Tom Borgstrom on May 10, 2009
Ed Sperling’s post at the System-Level Design Community revives a methodology topic that I think many verification teams are growing tired of and wish would get resolved. As Ed points out, the discussion of xxM verses yyM often devolves into a “religious” debate. This debate reflects the strong desire of verification teams to achieve higher productivity, but does little to help realize the goal.
With verification environments for complex chips often over a million lines of code, the case for higher productivity through verification reuse and interoperable VIP is strong. A key enabler on this front is to have a single, standard verification methodology and library. The last thing verification teams want to do is rewrite big chunks of their verification environment to fit in a different methodology, or to add layers of additional complexity to bind multiple disparate methodologies in a “franken-vironment”.
The ultimate user goal – a single, standard verification methodology and library – must be driven by an independent organization with an open and transparent process. The good news is that the verification community has recognized this and is well on its way to achieve this goal. For the past year or so, a technical working group at Accellera composed of chip designers and EDA vendors have been working furiously to develop standards for verification interoperability and ultimately a single, standard methodology. The process isn’t easy or fast, but progress is being made. Synopsys, for its part, has made significant contributions both in terms of technology and people to help support this process.
In the mean time, verification teams have to continue getting their chips out. Many take advantage of the productivity benefits of a vendor-supported methodology like the VMM, including advanced methodology applications, extensions into new domains, focused R&D investment and a worldwide support infrastructure.
Standards will come. In the mean time, get that chip verified!
Who knows what the future will bring! After implementing neural networks in analog CMOS for my MSEE at Ohio State, I moved to Japan to do digital ASIC design using the new VHDL language and fancy logic synthesis technology from a startup called Synopsys. This introduced me to the wonderful world of EDA, where I was able to explore lots of other cool new technologies from test automation at CrossCheck to FPGA synthesis at Exemplar to code coverage at TransEDA to testbench automation and methodology at Synopsys. Twenty years flew by in the blink of an eye!
I am starting a new exploration around the bigger picture of what it takes to verify and validate increasingly complex designs on increasingly compressed schedules and budgets. This broad topic ranges from technology to economics, from embedded software development and architecture analysis to RTL and circuit design; from personal productivity to distributed team efficiency; from novel ideas to fundamental paradigm shifts; from historical perspectives to predictions of future requirements. Please join me and share your thoughts on verification!
- Tom Borgstrom