Posted by Tom Borgstrom on May 5, 2009
If you are going to DAC this year, you may be interested in attending the panel System Prototypes: Virtual, Hardware or Hybrid that I’ve been organizing with Eshel Haritan of CoWare. We’ve got a great lineup of panelists from Amicus Wireless, Synopsys, Qualcomm, ST-Ericsson, LSI and CoWare who will debate the pros and cons of SystemC TLM-2.0 based virtual platforms, FPGA-based rapid prototypes or hybrids of the two for system prototyping. I’ve had a chance to peek at the panelist’s positions – all I can say now is that it promises to be a very lively discussion! Ron Wilson of EDN will moderate.
Tuesday July 28, 10:30am – 12:00pm; Room 102, Moscone Convention Center, San Francisco.
Who knows what the future will bring! After implementing neural networks in analog CMOS for my MSEE at Ohio State, I moved to Japan to do digital ASIC design using the new VHDL language and fancy logic synthesis technology from a startup called Synopsys. This introduced me to the wonderful world of EDA, where I was able to explore lots of other cool new technologies from test automation at CrossCheck to FPGA synthesis at Exemplar to code coverage at TransEDA to testbench automation and methodology at Synopsys. Twenty years flew by in the blink of an eye!
I am starting a new exploration around the bigger picture of what it takes to verify and validate increasingly complex designs on increasingly compressed schedules and budgets. This broad topic ranges from technology to economics, from embedded software development and architecture analysis to RTL and circuit design; from personal productivity to distributed team efficiency; from novel ideas to fundamental paradigm shifts; from historical perspectives to predictions of future requirements. Please join me and share your thoughts on verification!
- Tom Borgstrom