Photonic systems all have one thing in common: they need a light source. Photonic ICs (PICs) have been traditionally manufactured using group III-V semiconductor materials like Indium Phosphide (InP), since these are direct-bandgap materials that easily facilitate photons needed to generate light. The III-V PICS work well, but they tend to be expensive since the materials are brittle, which makes them difficult to handle in volume manufacturing and requires robust packaging.
In the last ten years, there has been a big push to reduce photonic system costs by moving to silicon-based (Si) photonics that can share the same wafer processing used for CMOS ICs. This enables low-cost chip manufacturing since the wafers are much more robust, processing equipment is well understood, and capital expenditures for electrical ICs can be leveraged for photonics.
One problem, however, is that Si is not a direct band-gap material, making it very difficult to use to create lasers, semiconductor optical amplifiers (SOAs), or other gain elements. Thus, the industry began searching for ways to integrate the best III-V lasers and gain elements with Si. The traditional solution to this problem, and how most of photonic systems are built today, has been to use discrete III-V laser chips and other optical components to create and amplify light and then bring that light into the Si PIC using optical fiber, usually by aligning the fiber with grating structures on the PIC to guide the light into the horizontal plane of the Si PIC.
While this approach works (and is used in all data centers today), it comes with its own share of problems. For example, roughly one-third of power is lost at every interface between laser, fiber, and PICs. To compound the issue, each photonic device on the PIC also has insertion loss and eventually, if you string together enough components, you run out of power. This limits design complexity that can be supported. In addition, the waveguides used in PICS are small and can only carry so much power, so you can’t simply turn up the laser power to accommodate for all the losses because this would damage the PIC.
Even with the cheaper silicon-based PICs, the cost of the overall photonic systems has not come down as desired since lasers, fibers and PICs must all be carefully aligned to transfer light from one to the other. This implies expensive manufacturing processes and a system that is difficult to use in harsh environments with large temperature swings, vibrations, or anything that could put the system out of alignment. Another problem is that individual lasers and fibers take up space in the system and each comes with their own probabilities of failure over time. The more discrete parts there are in a system, the higher the probability of failure caused by any one of them.
Efforts have been made to reduce cost and SWaP (size, weight, and power) of photonic systems by trying to integrate lasers more tightly with Si PICs. Epitaxial growth of III-V materials on Si has proven problematic due to different lattice structures and dislocations caused by defects in the materials.
Some companies have successfully etched holes in Si PICs and then bonded III-V laser chiplets into the holes, leaving a small air gap between the laser and the waveguides of the PIC. This works well, but the manufacturing process is complex since it requires very precise 3D alignment of the bonded chip to align the output of the laser with the Si waveguides. Designers must pay special attention to the interface facets of the laser and the PIC to avoid unwanted reflections and loss. Nonetheless, the method does replace two lossy transitions (laser to fiber and fiber to PIC) with one less lossy transition, and it removes optical fibers to simplify system assembly.
Processing of epi-stacks.
Figure courtesy of OpenLight Photonics
About a decade ago, a new method evolved in which individual III-V PIN structures were patterned as epi-stacks on a III-V wafer. These epi-stacks are the base layers for building lasers and other active devices. Instead of processing the full devices, the epi-stacks are diced from the III-V wafer and bonded onto specific areas of the Si PICs after the silicon waveguides and passive elements have been patterned, but before the Si PICs are diced from the Si wafer. The substrate of the epi-stacks is removed, and standard wafer processing is employed to pattern the active materials on these epi-stacks. All active materials and their interfaces to Si waveguides are made using lithography, which removes the need for critical alignment steps as well as the lossy interface between the III-V and Si devices. All processing is done at wafer scale to reduce costly manufacturing steps. Until recently, this methodology was primarily only employed by Intel, who used it internally for their photonic transceiver products.
In 2022, a start-up company called OpenLight Photonics partnered with Tower Semiconductor to introduce a commercially available silicon photonics platform with integrated lasers. OpenLight licenses their process technology to Tower Semiconductor along with specialized photonic IP in the form of integrated lasers, SOAs, EAM modulators and advanced photodiodes. Tower combines these devices with passive Si photonic devices and makes them available for designers to use through a photonics process design kit (PDK).
Example of transceivers with lasers heterogeneously integrated on PIC.
Figure courtesy of OpenLight Photonics
This heterogeneous integration of lasers and active gain elements in a silicon-based photonic offering has many benefits:
Reduced SWaP: All lasers, SOAs and active devices are integrated on the silicon PIC to remove multiple discrete photonic components and fiber, and reduce overall system size, weight, and power. Removing lossy interfaces between components also improves power efficiency.
Reduced photonic system costs: Reduced SWaP and the ability to process all active III-V devices along with passive devices at the Si-wafer-level reduces packaging and board assembly costs and simplifies manufacturing logistics by removing the need to source and package separate lasers and SOAs.
Improved reliability and yield: Yield and reliability increase as the number of discrete components is reduced. Pick and place accuracy requirements are relaxed as devices are created and aligned automatically through standard lithography. Standard layer processing also stabilizes the III-V epi sections on the silicon wafer.
Enables arbitrary circuit complexity: Circuits of arbitrary complexity are enabled as optical signals can be amplified anywhere needed to combat device insertion loss. The flexible design and manufacturing flow allows III-V active devices to be placed strategically on the Si die as needed for circuit performance. PIC architectures can include redundant components that can be switched if components fail, which increases overall reliability.
Optimized EPI Stacks: Epi-stacks can be optimized for different types of active devices and individually placed on the target Si die as dictated by the design. This adds additional performance capabilities to the photonics platform.
Synopsys Photonic Design Platform
The new integrated technology available to designers through a Tower Semiconductor PDK is optimized to work with Synopsys photonic design tools and multi-project wafer runs. The Synopsys OptoCompiler photonic design platform employs the rigor of standard electronic design automation tools and methodologies to enable co-design of electronic and photonic designs. The platform uses Synopsys OptoCompiler schematic-driven-layout (SDL), Synopsys OptSim photonic circuit-level simulation, and Synopsys IC Validator photonic design rule checking (DRC) and layout-vs-schematic (LVS) tools in a flow that resembles that which is used in a typical analog/mixed-signal design.
Combining state-of-the-art design automation tools and arbitrary circuit complexity as supported by the OpenLight process enables a broad applicable use space for integrated photonics, such as in datacom, telecom, LiDAR, healthcare, sensing, high-performance computing, AI, and optical computing.
Synopsys will demonstrate its support for this new technology on March 7-9 in Booth #2229 at the Optical Fiber Communications Conference and Exposition (OFC) in San Diego.
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